Michael J. Zierak

A 0.18 /spl mu/m BiCMOS technology featuring 120/100 GHz (f/sub T//f/sub max/) HBT and ASIC-compatible CMOS using copper interconnect

A BiCMOS technology is presented that integrates a high performance NPN (f/sub T/=120 GHz and f/sub max/=100 GHz), ASIC compatible 0.11 /spl mu/m L/sub eff/ CMOS, and a full suite of passive elements. Significant HBT performance enhancement compared to previously published results has been achieved through further collector and base profile optimization guided by process and device simulations. Base transit time reduction was achieved by simultaneously increasing the Ge ramp and by limiting the base diffusion with the addition of carbon doping to SiGe epitaxial base. This paper describes IBMs next generation SiGe BiCMOS production technology targeted at the communications market.

Foundation of rf CMOS and SiGe BiCMOS technologies

This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

A 0.24 /spl mu/m SiGe BiCMOS mixed-signal RF production technology featuring a 47 GHz f/sub t/ HBT and 0.18 /spl mu/m L/sub ett/ CMOS

A new base-after-gate integration scheme has been developed to integrate a 47 GHz f/sub t/, 65 GHz F/sub max/SiGe HBT process with a 0.24 /spl mu/m CMOS technology having 0.18 /spl mu/m L/sub eff/ and 5 nm gate oxide. We discuss the benefits and challenges of this integration scheme which decouples the HBT from the CMOS thermal cycles. We also describe the resulting 0.24 /spl mu/m SiGe BiCMOS technology, BiCMOS 6HP, which includes a 7 nm dual gate oxide option and full suite of passive components. The technology provides a high level of integration for mixed-signal RF applications.

High performance, low complexity 0.18 /spl mu/m SiGe BiCMOS technology for wireless circuit applications

High frequency performance at low current density and low wafer cost is essential for low power wireless BiCMOS technologies. We have developed a low-complexity, ASIC-compatible, 0.18 /spl mu/m SiGe BiCMOS technology for wireless applications that offers 3 different breakdown voltage NPNs; with the high performance device achieving F/sub t//F/sub max/ of 60/85 GHz with a 3.0 V BV/sub CEO/. In addition, a full suite of high performance passive devices complement the state-of-the-art SiGe wireless HBTs.

Integrated 85V rated complimentary LDMOS devices utilizing patterned field plate structures for best-in-class performance in network communication applications

This paper presents complimentary 85V-rated LDMOS devices integrated in a 180nm power management technology platform. The devices are fabricated using a design technique which utilizes tapered dielectric regions in combination with patterned floating field plated structures. The performance of the new structures are compared to conventional LDMOS structures and it shown that the floating field plated structures have superior BV_ds-R_{on, sp}, HCI reliability, and forward safe operating area figures-of-merit. These devices exhibit best-in-class BV_ds-R_{on, sp} figure-of-merit (NLDMOS : BV_ds=130V/R_{on, sp}=195mΩ.mm² and PLDMOS : BV_ds=140V/R_{on, sp}=530mΩ.mm²) and hot carrier reliability in excess of 10 years analog lifetime for rated V_DS = 85V and full range of V_GS. These devices enable cost effective integration of PoE systems with multiple interface channels and auxiliary switching regulators.

A high-resistivity SiGe BiCMOS technology for WiFi RF front-end-IC solutions

We present for the first time a novel high resistivity bulk SiGe BiCMOS technology that has been optimized for a WiFi RF front-end-IC (FEIC) integration. A nominally 1000 Ohm-cm p-type silicon substrate is utilized to integrate several SiGe HBTs for power amplifiers (PAs), a SiGe HBT low-noise amplifier (LNA), and isolated nFET RF switch device. Process elements include trench isolation for low-loss passives and reduced parasitic coupling, and a lower-resistivity region for the FETs to minimize changes to the circuit library.

High-resistivity SiGe BiCMOS technology development

IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS technology in 2011. This technology was optimized for WiFi and cellular NPN power amplifier (PA), NPN low noise amplifier (LNA), and isolated CMOS NFET switch rf front-end-IC (FEIC) integration. It includes an optional through silicon via used as a low inductance ground path for NPN emitters. Data for 50 Ω-cm, 1st generation HiRES, and 2nd generation HiRES NPN PA, LNA, and CMOS NFET switch devices are reviewed.

Fully-isolated silicon RF LDMOS for high-efficiency mobile power conversion and RF amplification

In this paper a fully isolated bulk Si RF LDMOS device platform is reported which has been optimized for highly efficient mobile power conversion and RF power amplification. The self-aligned RF LDMOS NFET achieves a specific on-resistance Rds, on of 0.94 ohm-mm2, a breakdown voltage >9V, an Rsp*Qgg product of 8.3 mohm nC, and a cutoff frequency Ft > 43 GHz. Complementary PFET RF LDMOS exhibit an Rds, on of 3.6 ohm-mm2 with a cutoff frequency Ft > 16GHz. Integrated DC-DC SMPS fabricated with these RF LDMOS have a 2.3x area reduction over conventional 5V CMOS and a gate driver efficiency increase of at least 75%. RF LDMOS NFET power amplifier cores (RF PA) under CW load pull and 3.3V supply voltage exhibit gains (Gt) of 18dB and 12dB at 2.4GHz and 5.8GHz, respectively, with a 1dB compression power density of 22dBm/mm of gate width and a maximum PAE > 70%. RF LDMOS power cells meet the 802.11n spectral mask requirement for a 20MHz 64 QAM modulated signal with Pout = 19dBm. These DC and RF results are the best reported for integrated Si LDMOS device structures, enabling the next generation of highly efficient miniaturized mobile power converters and new RF integration paradigms for mobile front-end modules.

A 19DBM 5.8GHzz PA demonstrator with a novel low ron high FT RF LDMOS

In this paper, we introduce an isolated RF LDMOS NFET is for RF Power Amplifier (PA) and power management applications. The RF LDMOS NFET has demonstrated a drain-source turn-on resistance (Rds,on) of 1.45ohm-mm, a cutoff frequency (Ft) greater than 40GHz and a drain-source breakdown down voltage (BV) in excess of 9V. For PA designs, the isolation layer is floating to reduce the parasitic and achieve high PAE/nonlinearity performance. RF power amplifier cores were fabricated and measured at 2.4GHz and 5.8GHz to demonstrate the RF LDMOS performance in PAs. Under CW loadpull and 3.3V supply, 18dB and 12dB gains (Gt) are achieved at 2.4GHz and 5.8GHz respectively, with 1dB compression point power density at 22dBm/mm gate width, and PAE > 63%, maximum PAE > 70%. Due to good model to hardware Pout correlation in a 5.8GHz PA cell, a fully matched PA last stage with the load-pull fundamental and harmonic impedances showed a less than 4° AM-PM phase distortion, meeting the 802.11n spectral mask requirement with 20MHz 64QAM modulated signal at 19dBm Pout.

A 0.24 μm SiGe BiCMOS technology featuring 6.5V CMOS, f T /f MAX of 15/14 GHz VPNP, and f T /f MAX of 60/125 GHz HBT

For the first time, we report a 0.24 mum SiGe BiCMOS technology that offers full suite of active device including three distinct NPNs, a vertical PNP, CMOS supporting three different operating-voltages, and wide range of passive devices. In particular, this technology provides 6.5 V CMOS capability and VPNP with fT/fMAX of 15/14 GHz and BVCEO of 6.5 V which can be used to complement high breakdown NPN with fT of 30 GHz and BVceo of 6.0 V.