Sarathy Rajagopalan

Development of 50mm Flipchip Plastic Ball Grid Array Package with Low-K Silicon Technology

The Flipchip Plastic Ball Grid Array (FPBGA) package has seen explosive growth in the last few years due to its excellent electrical and thermal performances. In order to fulfill the requirements of increasing number of Inputs/Outputs (I/Os) with enhanced electrical performance, a full array 50mm FPBGA was designed and developed in conjunction using silicon technology with copper (Cu) metallization and low-k dielectric. In flip-chip packages, the most critical material is the underfill. The challenge is further enhanced by low-k dielectric and large die size. Due to its close proximity to the inner layers of the silicon die, the underfill material influences the stress conditions at the low-k layers of the silicon. Hence, the underfill material and its associated processes play a big role in determining the reliability of the silicon in the flip-chip package. This paper summarizes the process and package development of 50mm FPBGA with low-k dielectric material. The process and underfill development work are described and discussed. The package level reliability qualification tests and results are presented. Upon completion of the package level qualification, a board level reliability study was pursued to demonstrate the assembly and rework capability for the 50mm FPBGA package. The information of the package construction, printed circuit board design/layout, and accelerated thermal cycle (ATC) test are provided. The resulting Weibull distribution plot of solder joint fatigue is generated.