Sarvesh H. Kulkarni

A 1.1 GHz 12

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum2 low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.

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A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm2 low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. The measured bitcell leakage from the SRAM array is ~2pA/b at retention voltage with integrated leakage reduction schemes.

A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A 4 kb high-density PROM array featuring the first high-volume manufacturable metal-fuse technology in 32 nm high-k metal-gate CMOS is introduced. In contrast to traditional salicided polysilicon based 2-D fuse cells, the metal-fuse technology enables a 3-D cell topology with program device and fuse element stacked on each other, achieving a 1.37 μm2 cell footprint. The 128-row by 32-column array with an asymmetric tunable static sense scheme can operate down to 0.5 V and provides multi-bit programming capability. Programming success using a 2 V-1 μs pulse condition is demonstrated. The technology is scalable and maintains full compatibility with modern high-k metal-gate processes.

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smallest reported one-transistor one-capacitor (1T1C) bit cell area measuring 1.01μm2. The 32-row by 32-column array with a programmable sensing scheme demonstrates yield exceeding 99.9% and robust reliability.

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37

The first metal-fuse technology in 22 nm tri-gate high-k metal-gate CMOS technology is presented. The memory technology offerings in high-volume manufacturing include a 2.05 μm2 2.2 V programmable high-density and a 16.4 μm2 1.6 V programmable low-voltage (LV) 1T1R bit cell. The LV operability of the technology allows the fuse arrays to be coupled with power delivery circuits operating at standard logic voltage levels. A charge pump voltage doubler operating on a 1 V voltage rail is demonstrated in this paper with healthy fusing yield.

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The 18-way set-associative, single-ported 9 MB cache for the Itanium/spl reg/2 processor, presented in this paper, uses 210 identical 48 kB sub-arrays with a 2.21 /spl mu/m/sup 2/ cell in a 0.13 /spl mu/m 6M CMOS technology. A staged mode ECC scheme avoids a latency increase in the L3 tag. A high Vt implant improves the read stability and reduces the sub-threshold leakage.

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This paper introduces the first high-volume manufacturable (HVM) metal-fuse technology in a 14-nm trigate high-k metal-gate CMOS process. A high-density array featuring a 0.9-μm² bit cell with an efficient bit level redundancy scheme is presented. An array efficiency of over 53% is achieved through hierarchical bitline design by minimizing the impact of parasitic resistance on fuse programming through short local bitline and sharing sense amplifier through longer global bitline. A power gating-based scheme is adopted to reduce leakage current consumption and high-voltage exposure to minimize reliability concern. Program conditions can be optimized for HVM and in-field programming to achieve close to 100% unit level yield with the proposed redundancy scheme.

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This work introduces the first high-volume manufacturable (HVM) metal-fuse technology in a 14nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 0.9μm2 1T1R bit cell and bit level redundancy is presented. An array efficiency of 50% is achieved with hierarchical bit line design to separate fuse programming from read/sense. A power gating scheme is adopted to reduce leakage current consumption and reduce high voltage exposure for reliability. Program conditions can be optimized for HVM and in-field programming (IFP) to achieve close to 100% bit level yield.