Satoshi Takaya

A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing

Three dimensional (3D) stacking of memory chips is a promising direction for implementing memory systems in mobile applications and for low-cost high-performance computation. The requirements are extremely low power consumption, high data bandwidth, stability and scalability of operation, as well as large storage capacity with a small footprint. A digital control chip at the base of the stack is needed to efficiently access the 3D memory hierarchy, as well as to emulate a standard memory interface for compatibility. The overall performance and yields of a 3D system are constrained by vertical communication channels among the stacked chips, as well as the connections to the PCB. However, the empirical models presently used in the design stage do not properly represent the electrical and mechanical properties and performance variations of through silicon vias (TSVs) and microbumps (μBumps). What is needed are circuit techniques that handle such uncertainties to enable the creation of robust 3D data links. This paper presents a complete test vehicle for TSV-based wide I/O data communication in a three-tier 3D chip stack assembled in a BGA package. In-place eye-diagram and waveform capturers are mounted in an active silicon interposer to characterize vertical signaling through the chain of TSVs and μBumps.

An on-chip continuous time power supply noise monitoring technique

A continuous-time power supply noise monitoring technique features a coverage of voltage domains at Vdd as well as at Vss and multi-channel probing at more than a hundred locations on power planes in a circuit. Methods toward quality on-chip power supply noise measurements are derived. A calibration flow eliminates the offset as well as gain errors among probing channels. A combined evaluation of on-chip measurements and off-chip circuit simulation precisely characterizes probing performance. In addition, consistency was ensured among noise waveforms captured by sampled-time precise digitization and by the proposed continuous-time monitoring. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with ± 200 mV at 1.2 and 0.0 V, respectively, with less than 3 mV offset voltages among 240 probing channels, and with the effective bandwidth of 1.0 GHz.

On-chip sine-wave noise generator for analog IP noise tolerance measurements

A sine-wave noise generator with a harmonic-eliminated waveform is proposed for measuring the noise tolerance of analog IPs. In the waveform, harmonics up to the thirteenth harmonic are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. This waveform includes only high-region frequency harmonic components which are easily suppressed by a low-order filter. In the circuit, the harmonic-eliminated waveform generator is combined with a current-controlled oscillator and a frequency-adjustment circuit. The sine-wave noise generator can generate power-line noise from 20 MHz to 220 MHz in 1 MHz steps. A spurious-free dynamic range (SFDR) of 45 dB is obtained at the 100 MHz noise frequency.

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan

A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor is reported. Multiple touch points are detected by a two-step dual-mode capacitance scan, where self- and mutual-capacitance measurements are hierarchically performed in two steps to reduce scan time that is otherwise increased due to high resolution. 160 dedicated row and column ADCs are used for the parallel read-out to further reduce scan time. A time-domain digital conversion that uses a counter-based slope ADC significantly reduces power and area for the parallel ADC approach. The signal attenuation due to the sensor capacitance reduction in the 1mm fine-pitch electrode is compensated by using thorough noise-reduction techniques in the sensor analog front-end (AFE). A 0.35μm CMOS prototype demonstrates 41dB SNR with >3× higher pitch resolution, >10× faster touch-point scan, 12× and 4× higher energy and area efficiency compared to state-of-the-art touch sensors [1,2].

In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking

Three-dimensional chip stacking technologies have rapidly progressed in market deployments, calling the strong needs for design and validation techniques of 3-D integrated circuits (ICs). This paper proposes the hybrid of at-speed testing and waveform-based diagnosis for searching the optimum and stable operating conditions of 3-D ICs in an adaptive way to electric properties of a stacked chip structure. A functional silicon interposer features in-place waveform capturing and diagnosis for the quality of signaling and the integrity of power distribution networks (PDNs) deeply within a 3-D chip stack. In-place captured waveforms and eye diagrams are experimentally demonstrated and prove a solid data link operation through vertical TSV channels of 4096-b wide input/output (I/O) bus at the rate of 100 GB/s. While the built-in at-speed self-test functions confirm the bit error rates, the waveform-based diagnosis provides the optimum selection of driving strengths among mini I/O transceivers. The test and diagnosis features therefore play individual roles in validating 3-D IC operations, and exhibit strong correlations in their respective measurements.

Accurate analysis of substrate sensitivity of active transistors in an analog circuit

A substrate network tailored for a variety of transistor geometry including channel sizes, fingering and folding, and shapes and placements of guard bands, extends the capability and accuracy of full-chip noise coupling analysis of mixed technology VLSI integration. Analysis of substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 64 different geometry and operating conditions well agrees with on-chip substrate coupling measurements, with the discrepancy within 3 dB.

On-chip in-situ measurements of V th and AC gain of differential pair transistors

In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, Vth, of 1.0-V transistors in a 90-nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC response of the same amplifier. The distribution of AC gain versus Vth of transistors within amplifiers is captured. The degradation of common-mode rejection property is observed for an amplifier with intentionally introduced mismatches to the pair of transistors.

Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs

A three tier, three dimensional chip stack forms wide I/O test vehicle and demonstrates 100 GByte/sec in vertical data channels with 4096 bit TSVs. The operation is stable for the wide range of supply voltage from 0.75 V to 1.2 V. An in-place waveform capture and a built-in self test mechanism embody on-chip diagnosis of high-bandwidth data transmissions, by monitoring signal waveforms as well as measuring eye openings and bit error rates.