Yoji Bando

An on-chip continuous time power supply noise monitoring technique

A continuous-time power supply noise monitoring technique features a coverage of voltage domains at Vdd as well as at Vss and multi-channel probing at more than a hundred locations on power planes in a circuit. Methods toward quality on-chip power supply noise measurements are derived. A calibration flow eliminates the offset as well as gain errors among probing channels. A combined evaluation of on-chip measurements and off-chip circuit simulation precisely characterizes probing performance. In addition, consistency was ensured among noise waveforms captured by sampled-time precise digitization and by the proposed continuous-time monitoring. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with ± 200 mV at 1.2 and 0.0 V, respectively, with less than 3 mV offset voltages among 240 probing channels, and with the effective bandwidth of 1.0 GHz.

A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design

A fully integrated framework of full-chip power and substrate noise analysis is discussed, featuring description of transistor-level custom circuits as dynamic noise sources, a high capacity solver for chip-level substrate coupling, and noise back annotation flow to transistors of sensitive circuits. Recursive evaluation of power current and operation timing under the presence of dynamic IR drop greatly improves the accuracy of analysis. A 90-nm CMOS chip was examined both by on-chip noise measurements and full-chip noise analysis.

On-chip sine-wave noise generator for analog IP noise tolerance measurements

A sine-wave noise generator with a harmonic-eliminated waveform is proposed for measuring the noise tolerance of analog IPs. In the waveform, harmonics up to the thirteenth harmonic are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. This waveform includes only high-region frequency harmonic components which are easily suppressed by a low-order filter. In the circuit, the harmonic-eliminated waveform generator is combined with a current-controlled oscillator and a frequency-adjustment circuit. The sine-wave noise generator can generate power-line noise from 20 MHz to 220 MHz in 1 MHz steps. A spurious-free dynamic range (SFDR) of 45 dB is obtained at the 100 MHz noise frequency.

Accurate analysis of substrate sensitivity of active transistors in an analog circuit

A substrate network tailored for a variety of transistor geometry including channel sizes, fingering and folding, and shapes and placements of guard bands, extends the capability and accuracy of full-chip noise coupling analysis of mixed technology VLSI integration. Analysis of substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 64 different geometry and operating conditions well agrees with on-chip substrate coupling measurements, with the discrepancy within 3 dB.

On-chip in-situ measurements of V th and AC gain of differential pair transistors

In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, Vth, of 1.0-V transistors in a 90-nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC response of the same amplifier. The distribution of AC gain versus Vth of transistors within amplifiers is captured. The degradation of common-mode rejection property is observed for an amplifier with intentionally introduced mismatches to the pair of transistors.

Microprocessor power noise measurements with different levels of resource occupancy

Power noise waveforms of a 32-bit microprocessor were on-chip measured in a 90-nm CMOS technology. A dedicated measurement system combines an embedded programming environment and a measurement flow that ensures acquisition of noise waveforms during designated arithmetic operation. Power noise exhibits clear relation with the contents of computation, where the magnitude of power noise reflects the occupancy ratio of computing resources of a microprocessor. The level of correlation is shown to be different among static and dynamic portions of power noise. It is concluded that practical power noise analysis requires the higher-level abstraction of a large-scale integrated digital system.

Chip-to-chip half duplex data communication at 135 Mbps over power-supply rails

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at 135 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by more than 30 dB, purifying power supply current for internal circuits. Chip-to-chip power line communication invokes supplementary diagnosis functionality to be embedded in SoCs at the time of power connection, with the reduced cost of pin counts.