Satoshi Uemori

Stochastic TDC architecture with self-calibration

This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3) Stochastic architecture for fine time resolution. (4) Self-testing for reliability requirements. These features can be implemented with an advanced fine CMOS process using digital design methodology. The circuit structure and operation are described, and MATLAB simulation results are presented.

Low-Distortion Single-Tone and Two-Tone Sinewave Generation Algorithms Using an Arbitrary Waveform Generator

This paper describes algorithms for generating low distortion single-tone and two-tone sine waves, for testing ADCs,using an arbitrary waveform generator (AWG). The AWGconsists of DSP and DAC, and the nonlinearity of the DACgenerates distortion components. We propose here to use DSPalgorithms to precompensate for the distortion. The DSP part of the AWG can interleave two or four signals with the same frequency but different phase at the input to the DAC, in order to precompensate for distortion caused by DAC nonlinearity. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of this approach.

ADC linearity test signal generation algorithm

This paper describes an algorithm for generating test signals to efficiently test the linearity of ADCs. Linearity is an important testing item for ADCs, and it takes a long time (hence is costly) to test low-sampling-rate, high-resolution ADCs. We here propose to generate a test signal consisting of multiple sine waves, to precisely test the linearity for specific important codes (such as around the center of the output codes), using an arbitrary waveform generator (AWG) and an analog filter. We have performed MATLAB simulation to validate our algorithm, and the results show that in some cases the testing time can be reduced to half that for conventional sine wave histogram testing.

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

This paper describes the architecture and principles of operation of sigma-delta ( ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit ΣΔ TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches.

SAR ADC that is configurable to optimize yield

This paper describes a non-binary SAR ADC architecture that is reconfigurable at production testing time to increase the number of chips that meet a given sampling speed specification, i.e. to improve yield. A non-binary SAR ADC can realize higher sampling rates than a comparable conventional binary SAR ADC, by using overlapping SA ranges so that any errors due to incomplete settling of the internal DAC can be corrected in later steps of the successive approximation. In general, using more of the overlapping successive- approximation (SA) steps (and faster steps) permits faster SAR ADC sampling rates but increases power consumption. Thus this power-speed tradeoff can be utilized to compensate for CMOS process variations of each ADC chip; if the chip is slow, we can use more-rapid SA steps and more overlapping steps to satisfy the sampling speed specification (at the cost of increasing power consumption); if the chip is fast, we can use fewer (and slower) steps to satisfy the sampling speed specification and also achieve lower power consumption. We use automatic test equipment (ATE) for production testing and to store the appropriate algorithm data that enables the sampling rate specification to be met in flash memory on the chip. The DAC output settling margin is determined by checking comparator output at each step and confirming that ADC final output is correct. Our measurements demonstrate the effectiveness of this approach.

Multi-bit sigma-delta TDC architecture with self-calibration

This paper describes the architecture and principles of operation of sigma-delta (ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications; they offer good accuracy with short test times. In particular, we describe a multi-bit ΣΔ TDC architecture for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose a self-calibration method that measures delay values using an improved ring oscillator circuit to improve the overall TDC linearity. Our MATLAB simulation results demonstrate the effectiveness of the proposed approach.

Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing Measurement

This paper describes the architecture (circuit design) and principles of operation of sigma-delta Sigma-Delta time-to-digital converters (TDC) for high-speed I/O interface circuit test applications, they offer good accuracy with short test times. In particular, we describe multi-bit ΣΔ TDC architectures for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose two methods to improve the overall TDC linearity: a data-weighted averaging algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our MATLAB and Spectre simulation results demonstrate the effectiveness of these approaches.

Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure

This paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However it suffers from nonlinearity, and hence needs calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for background calibration of the residue amplifier nonlinearity and gain error as well as the DAC nonlinearity all together with fast convergence, and validated its effectiveness by MATLAB simulation.