Satoshi Yusa

PROGRESS OF NIL TEMPLATE MAKING

Nano-imprint lithography (NIL) has been counted as one of the lithography candidates for hp32nm node and beyond and has showed excellent resolution capability with remarkable low line edge roughness that is attracting many researchers in the industry who were searching for the finest patterning technology. Therefore, recently we have been focusing on the resolution improvement on the NIL templates with the 100keV acceleration voltage spot beam (SB) EB writer and the 50keV acceleration voltage variable shaped beam (VSB) EB writer. The 100keV SB writers have high resolution capability, but they show fatally low throughput if we need full chip writing. Usually templates for resolution pioneers needed just a small field (several hundred microns square or so), but recently requirements for full chip templates are increasing. For full chip writing, we have also started the resolution improvement with the 50keV VSB writers used in current 4X photomask manufacturing. The 50keV VSB writers could generate full chip pattern in a reasonable time though resolution limits are inferior to that with the 100keV SB writers. In this paper, we will show latest results with both the 100keV SB and the 50keV VSB EB writers. With the 100keV SB EB writer, we have achieved down to hp15nm resolution for line and space pattern, but found that to achieve further improvement, an innovation in pattern generation method or material would be inevitable. With the 50keV VSB EB writer, we have achieved down to hp22nm resolution for line and space pattern. Though NIL has excellent resolution capability, solutions for defect inspection and repair are not clearly shown yet. In this paper, we will show preliminary inspection results with an EB inspection tool. We tested an EB inspection tool by Hermes Microvision, Inc. (HMI), which was originally developed for and are currently used as a wafer inspection tool, and now have been started to seek the application for mask use, using a programmed defect template.

Development of attenuating PSM shifter for F2 and high-transmission ArF lithography

A new att-PSM shifter for both F2 and high-transmittance ArF lithography was developed. This shifter consists of SiON / TaHf in stacked layers. SiON for phase shift layer has a moderate transmittance and refractive index, and has sufficient laser durability. The TaHf film, which is a transmittance control layer, was effective as a functional layer in mask dry etching. Adopting the 3 step etching procedure, low damage of the quartz surface and less impact to CD shift was realized. It was confirmed that a new shifter has also sufficient feasibility to the mask inspection and repair process.

Study of program defects of 22nm nanoimprint template with an advanced e-beam inspection system

Nanoimprint lithography (NIL) is a candidate of alternative, low cost of ownership lithography solution for deep nano-meter device manufacturing12. For the NIL template pattern making, we have been developing the processes with 100keV SB EB writer and 50keV VSB EB writer to achieve the fine resolution of near 20nm1-7. However, inspection of nanoimprint template posed a big challenge to inspection system due to the small geometry, 1x comparing to 4x of Optical mask and EUV mask. Previous studies of nanoimprint template inspection were performed indirectly on a stamped wafer and/or on a round quartz wafer13. Electron beam inspection (EBI) systems have been widely used in semiconductor fabs in nanometer technology nodes. Most commonly EBI applications are electrical defects, or voltage contrast (VC) defects detection and monitoring8-11. In this study, we used a mask EBI system developed by Hermes Microvision, Inc. (HMI) to directly inspect a NIL template with line/space and hole patterns half pitched from 22nm to 90nm and with program defects sized from 4nm to 92nm. Capability of inspection with 10nm pixel size has been demonstrated and capability of capturing program defects sized 12nm and smaller has been shown. This study proved the feasibility of EBI as inspection solution of nanoimprint template for 22nmHP and beyond.

200-mm EPL stencil mask fabrication and metrology

200-mm electron-beam projection lithography (EPL) masks were fabricated starting from stress-controlled silicon-on-insulator (SOI) substrates. The internal stress of the SOI layer is controlled to be ca. 10 MPa by B doping. The blank fabrication process has been established by the Bosch deep trench etch process. EB patterning was done on a JEOL JBX9000MVII with a positive-tone chemically amplified resist of 400-nm thickness. Resist image of 200-nm wide lines-and-spaces pattern was transferred to 2-um thick SOI layer by a shallow trench etching. A dual-mode critical dimension (CD)-SEM was implemented, and used for mask characterization. Preliminary results on uniformity of CD-shift in the dry etching and final CD were reported. 200-mm EPL masks with a gate layer of a system-on-chip device pattern were fabricated.

UV NIL mask making and imprint evaluation

UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the finest patterns. We have been focused on the resolution improvement in mask making, and with a 100kV acceleration voltage EB writer process, we have achieved down to 18nm resolution, and have established a mask making process to meet the requirements of the pioneers. Usually such masks needed just a small field (several hundred microns square or so). Now, UV NIL exploration seems to have reached the step of feasibility study for mass production. Here, instead of a small field, a full chip field mask is required, though the resolution demand is not as tough as for the extremely advanced usage. The 100kV EB writers are adopting spot beams to generate the pattern and have a fatally low throughput if we need full chip writing. In this work, we focused on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing. The 50kV VSB writers can generate full chip pattern in a reasonable time, and by choosing the right patterning material and process, we could achieve resolution down to 32nm. Our initial results of 32nm class NIL masks with full chip field size will be shown and resolution improvement plan to further technology nodes will be discussed.

NIL template making and imprint evaluation

Nano-imprint lithography (NIL) is expected as one of the candidates for hp32nm to hp22nm technology nodes. NIL needs 1X patterns on masks and a transit from 4X to 1X means a big and hard technology jump for the mask industry. We have reported in previous papers that the resolution limit with 50keV acceleration voltage VSB (variable shaped beam) electron beam writer, which are used in current 4X photomask manufacturing, was around 65nm. And we have also reported that to reach the required resolution for hp32nm node, the usage of a 100keV acceleration voltage spot beam writer would be inevitable. Recently, we have installed a 100keV spot beam EB writer adjacent to our photomask manufacturing line. In this paper, we will present our initial results with the tool. We have confirmed, after tuning of our process, a stable resolution capability compatible for hp32nm. With this process, we have begun sample template manufacturing, and initial imprint results are also presented. Templates with hp28nm dense line patterns were fabricated and were well imprinted.

UV NIL template making and imprint evaluation

UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting pioneers in the industry who were searching for the finest patterns. We have been focused on the resolution improvement in NIL template making with a 100keV acceleration voltage spot beam EB writer process, and have established a template making process to meet the requirements of the pioneers. Usually such templates needed just a small field (several hundred microns square or so) Now, for several semiconductor devices, the UV NIL is considered not only as a patterning solution for R&D purpose but eventually as a potential candidate for production, and instead of a small field, a full chip field mask is required. Although the 100kV EB writers have excellent resolution capability, they are adopting spot beams (SB) to generate the pattern and have a fatally low throughput if we need full chip writing. In this paper, we are focusing on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X photomask manufacturing. The 50keV VSB writers can generate full chip pattern in a reasonable time, and by choosing the right patterning material and process, we achieved resolution down to hp28nm, and initial promising results of hp22nm (partial resolution) for line and spaces, and hp26nm for dense holes were observed..

UV-NIL templates for the 22nm node and beyond

NIL (nano-imprint lithography) is expected as one of the lithographic candidates for 32nm node and beyond. Recently, the small line edge roughness (LER) as well as the potentially high resolution that will ensure no-OPC mask feature is attracting many researchers. However, the NIL needs 1X patterns on template and a transit from 4X to 1X is a big and hard technology jump for the mask industry. The fine resolution pattern making on the template is one of the most critical issues for the realization of NIL. In this paper, as a continuation of our previous works1-5, we have achieved further resolution by optimizing the materials, their thicknesses, the developing and the etching processes, as well as the writing parameters of the 100keV SB (spot beam) writer. At the best resolved point on the template, resolutions down to hp (half pitch) 18nm on dense line patterns, hp20nm on dense hole patterns, and hp26nm on dense dot patterns were confirmed. Concerning stable pattern resolution over a certain field area, we evaluated pattern resolution through over a 250um square area, which we think would be adequate for initial imprint tests. For the 250μm square area, we confirmed pattern resolution of hp24nm for dense line patterns and hp32nm for dense hole patterns. In addition, we have studied resolution limit of the 50keV VSB (variable shaped beam) photomask production writing tools, which have been commonly used tools in the 4X photomask manufacturing for larger field size patterning. Materials, process conditions and parameters acquired through the 100keV SB process were implanted, and we could fabricate templates with hp32nm dense line patterns, with acceptable full chip uniformity and writing time. We also studied the imprint capability, and fabricated a template with fine features and imprinted it onto a wafer. As a result, we could transfer hp24nm dense line patterns, hp24nm dense hole patterns, and hp32nm dense dot patterns onto the wafer.

Image placement accuracy of single-membrane stencil masks for e-beam lithography

Three stencil masks with simple die layouts on 24 mm x 24 mm Si membranes are made to compare simulation and experiment on image placement (IP). A pseudo finite element (FE) modeling is adopted. Displacements predicted by simulation are found to be smaller than experimental values, but both agree qualitatively. Four stencil masks with die layouts that model on ULSI hole layers in 30% opening ratio and pattern arrangement are successfully made. Displacements are reduced to 1/4 by adopting IP correction. The IP correction of EB data is found to be a useful method of reducing IP error.

Experimental analysis of image placement accuracy of single-membrane masks for LEEPL

We have fabricated seven masks with different patterns on a 27 mm x 34 mm single-membrane for Low Energy Electron-beam Proximity Lithography (LEEPL) by the wafer-flow process. We have examined the membrane flatness and image placement (IP) accuracy, which are essential qualities to be assured. We summarize the results as follows: Masks with membranes of 13 MP and 20MPa stress satisfy the membrane flatness requirement of less than 2 μm while a mask with a 6 MPa membrane does not. Maps of the distortion induced by the wafer-flow process are obtained for the masks with 13 MPa and 20 MPa membranes and their performance is explained in terms of the contraction of the mask substrate. The out-of-plane distortion for a 3 mm x 3 mm block of dense hole patterns with an opening ratio, ranging from 10% to 40%, has been evaluated. The distortion induced by the block has been evaluated and the effect of the local magnification correction on the IP error is examined. Maps of the distortion induced by the wafer-flow process and 4 x 4 blocks of 10% and 20% opening are obtained for a mask with 13 MPa membrane and the distortion induced by the blocks is estimated in 3σ. The uncorrectable IP error for the mask with the blocks of 10% opening is estimated to be 10 nm (in 3σ), which satisfies the specification for LEEPL masks.