Satyavolu S. Papa Rao

GaAs on Si epitaxy by aspect ratio trapping: analysis and reduction of defects propagating along the trench direction

The Aspect Ratio Trapping technique has been extensively evaluated for improving the quality of III-V heteroepitaxial films grown on Si, due to the potential for terminating defects at the sidewalls of SiO2 patterned trenches that enclose the growth region. However, defects propagating along the trench direction cannot be effectively confined with this technique. We studied the effect of the trench bottom geometry on the density of defects of GaAs fins, grown by metal-organic chemical vapor deposition on 300 mm Si (001) wafers inside narrow (<90 nm wide) trenches. Plan view and cross sectional Scanning Electron Microscopy and Transmission Electron Microscopy, together with High Resolution X-Ray Diffraction, were used to evaluate the crystal quality of GaAs. The prevalent defects that reach the top surface of GaAs fins are {111} twin planes propagating along the trench direction. The lowest density of twin planes, ∼8 × 108 cm−2, was achieved on “V” shaped bottom trenches, where GaAs nucleation occurs only ...

Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

Copper contact metallization for 22 nm and beyond

We used Cu contact metallization to solve one of the critical challenges for 22 nm node technology. Cu contact metallization allowed us to demonstrate worlds smallest and fully functional 22 nm node 6T-SRAM [1]. Cu contact metallization was executed using CVD Ru-containing liner. We obtained early reliability data by thermally stressing bulk device. Bulk device parameters such as junction and gate leakage currents and overlap capacitance were stable after BEOL anneal stress. We also demonstrated the extendibility of Cu contact metallization using 15 nm contacts.

Epitaxial growth of GaSb and InAs fins on 300 mm Si (001) by aspect ratio trapping

We report on the monolithic integration of GaSb and InAs fins on on-axis 300 mm Si (001) by metal-organic chemical vapor deposition. The thickness of the GaAs/Si (001) fins used as a template is optimized to allow the formation of {111} facets and the confinement of defects generated at the GaAs/GaSb and GaAs/InAs interfaces by means of the aspect ratio trapping technique. Anti-phase domains are avoided via a careful design of the GaAs/Si interface. Threading dislocations in GaSb are controlled through the formation of an interfacial misfit dislocation array along the GaSb/GaAs [1¯11] and [11¯1] interfaces. Defects on InAs are controlled through the promotion of a two-dimensional growth, which spontaneously occurs on GaAs {111} planes. The results represent a step forward towards the integration of III–V nano-scale photonic and electronic components on a Si complementary metal-oxide-semiconductor compatible platform using a precisely engineered GaAs on Si template.

Reducing Time Dependent Line to Line Leakage Following Post CMP Clean

A systematic approach was taken to identify methods to prevent post CMP corrosion of copper in 22nm interconnect structures. Line to line current leakage measurements (at various times post CMP) were used as a means to quantify the extent and time-dependence of copper corrosion. Interruption of the corrosion mechanism by the use of passivating agents in post-CMP clean chemistries is explored. A broad-based screening was conducted to identify aqueous formulations of passivating agents for protection of copper which do not have deleterious effects on line resistance and overall defectivity. A formulation was identified which was effective in preventing corrosion when applied during post CMP brush clean.

Nondestructive Defect Characterization of Saw-Damage-Etched Multicrystalline Silicon Wafers Using Scanning Electron Acoustic Microscopy

Defects in multicrystalline silicon wafers after saw-damage etch (SDE) for different etch durations are characterized nondestructively using scanning electron acoustic microcopy (SEAM). SEAM is shown to be able to detect both surface and subsurface defects, as well as crystallographic imperfections such as grain boundaries in mc-Si wafers. The capabilities of the SEAM imaging are further extended for investigations of the structural properties of the saw-damage-induced defects and optimization of the SDE process. It is established that SEAM could be effective in determining the optimal SDE etch duration required for the minimization or complete removal of the saw-damage layer. In addition, it also confirms that the SDE process itself does not create new line-like defects.

Development and characterization of advanced process technologies for the fabrication of crystalline-Si solar cells

Photovoltaic devices were fabricated at IBM TJ Watson Research Center using a research line designed to run different substrate types concurrently. The process knowledge gained from CMOS IC fabrication is applied to solar cell fabrication to create cells with plated Cu front metallization, Al back contacts, and PECVD SiN ARC. The interaction between substrate type and process conditions for saw damage etch, PECVD SiN deposition and emitter formation (thermal budget exposure) is presented in this paper. Electroplating process characterization results are discussed. The effects on the electrical characteristics of the photovoltaic device due to the process parameters chosen, and due to extrinsic defects, are discussed.