Dennis R. Ball

Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design

A novel mechanism for upset is seen in a commercially available 0.25 /spl mu/m 10-T SEE hardened SRAM cell. Unlike traditional multiple node charge collection in which diffusions near a single event strike collect the deposited carriers, this new mechanism involves direct drift-diffusion collection at an NFET transistor in conjunction with parasitic bipolar conduction in nearby PFET transistors. The charge collection with the parasitic bipolar conduction compromise the SEE hardened design, thus causing upsets. The mechanism was identified using laser testing and three-dimensional TCAD simulations.

The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM

Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume of an SEU hardened SRAM. Simulation results show that materials external to the sensitive volume can affect the experimentally measured cross-section curve.

Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations.

Role of heavy-ion nuclear reactions in determining on-orbit single event error rates

Simulations show that neglecting ion-ion interaction processes (both particles having Z>1) results in an underestimation of the total on-orbit single event upset error rate by more than two orders of magnitude for certain technologies. The inclusion of ion-ion nuclear reactions leads to dramatically different SEU error rates for CMOS devices containing high Z materials compared with direct ionization by the primary ion alone. Device geometry and material composition have a dramatic effect on charge deposition in small sensitive volumes for the spectrum of ion energies found in space, compared with the limited range of energies typical of ground tests.

The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design.

Characterizing SRAM Single Event Upset in Terms of Single and Multiple Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAMs state is shown to be based upon the resistive path from the p+ -sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are predicted and compared to SRAM test data.

The effect of metallization Layers on single event susceptibility

We investigate the effects of metallization layers on the radiation hardness of an epitaxial CMOS memory technology using Monte Carlo simulations. A geometrically and compositionally realistic three-layer metallization scheme is employed in detailed radiation transport simulations that include contributions from discrete /spl delta/-rays and nuclear reactions. The presence of high-Z plugs used to connect different metallization layers can have a significant effect on the single-event sensitivity depending on the location of the high-Z material relative to the sensitive region of the underlying device.

Separation of ionization and displacement damage using gate-controlled lateral PNP bipolar transistors

Proton irradiation produces both ionization and displacement damage in semiconductor devices. In this paper, a technique for separating the effects of these two types of damage using a lateral PNP bipolar transistor with a gate contact over the active base region is described. By biasing the gate appropriately, the effects of ionization-induced damage are minimized and the effects of displacement damage can be measured independently. Experiments and simulations are used to validate this approach and provide insight into proton-induced BJT degradation.

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

Direct observation of fast-transient single event signatures often involves considerable uncertainty due to the limitations of monitoring circuitry. A built-in-self-test circuit for the measurement of single-event transients (SET) has been implemented in a 45 nm partially depleted silicon-on-insulator technology that allows for the extraction of measurement-induced uncertainty. SET pulse width data from heavy-ion experiments are provided and compared to technology computer aided design simulations. A method for compensating for the measurement bias and skew is provided.

Comparing Single Event Upset sensitivity of bulk vs. SOI based FinFET SRAM cells using TCAD simulations

The bulk and SOI FinFET SRAMs cells have comparable critical charges; however, the bulk cell has a lower upset LET threshold as well as larger sensitive cross section than the SOI cell. This implies a higher single event error rate in the bulk-based compared to SOI-based FinFET technologies.