Scott Preston Moore

Development of a Low CTE chip scale package

This paper describes the development of a low CTE organic Chip Scale Package (CSP) jointly by KST and IBM. Tests carried out on the low CTE laminate material and subsequently on the related CSP are described. The new material set, identified as Advanced SLC Package, combines low CTE core and build-up dielectric materials to achieve a composite laminate CTE of 9-12 ppm/°C, which is intermediate between the CTEs of silicon device and conventional board. The lower composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI) and white bumps. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. Global and chip-site warp data from thermo-mechanical modeling are compared to the measured warp data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated.

Connected ground and floating plane package design and electrical analysis

A multilayer chip carrier is described which utilizes high density thin film circuitization and polyimide dielectric in both connected ground and floating plane configurations. Processing deltas with respect to product design are also described, and the process efficiencies of the floating reference plane option are highlighted. Electrical models and simulations of both options and actual hardware measurements are presented and are compared to a non ground plane chip carrier design. Results show floating reference plane designs to exceed non-ground plane designs for simultaneous switch noise immunity and system speed. Connected ground plane designs are shown to provide the highest level of package performance. Floating plane products provide an intermediate performance level that may be desirable depending on application conditions and affordable cost.<<ETX>>