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Dive into the research topics where Scott W. Fong is active.

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Featured researches published by Scott W. Fong.


Advanced Materials | 2015

Significant Enhancement of Infrared Photodetector Sensitivity Using a Semiconducting Single‐Walled Carbon Nanotube/C60 Phototransistor

Steve Park; Soo Jin Kim; Ji Hyun Nam; Gregory Pitner; Tae Hoon Lee; Alexander L. Ayzner; Huiliang Wang; Scott W. Fong; Michael Vosgueritchian; Young Jun Park; Mark L. Brongersma; Zhenan Bao

A highly sensitive single-walled carbon nanotube/C60 -based infrared photo-transistor is fabricated with a responsivity of 97.5 A W(-1) and detectivity of 1.17 × 10(9) Jones at 1 kHz under a source/drain bias of -0.5 V. The much improved performance is enabled by this unique device architecture that enables a high photoconductive gain of ≈10(4) with a response time of several milliseconds.


Nano Letters | 2014

Ultrafast Characterization of Phase-Change Material Crystallization Properties in the Melt-Quenched Amorphous Phase

Rakesh Jeyasingh; Scott W. Fong; Jaeho Lee; Zijian Li; Kuo-Wei Chang; Davide Mantegazza; Mehdi Asheghi; Kenneth E. Goodson; H.-S. Philip Wong

Phase change materials are widely considered for application in nonvolatile memories because of their ability to achieve phase transformation in the nanosecond time scale. However, the knowledge of fast crystallization dynamics in these materials is limited because of the lack of fast and accurate temperature control methods. In this work, we have developed an experimental methodology that enables ultrafast characterization of phase-change dynamics on a more technologically relevant melt-quenched amorphous phase using practical device structures. We have extracted the crystallization growth velocity (U) in a functional capped phase change memory (PCM) device over 8 orders of magnitude (10(-10) < U < 10(-1) m/s) spanning a wide temperature range (415 < T < 580 K). We also observed direct evidence of non-Arrhenius crystallization behavior in programmed PCM devices at very high heating rates (>10(8) K/s), which reveals the extreme fragility of Ge2Sb2Te5 in its supercooled liquid phase. Furthermore, these crystallization properties were studied as a function of device programming cycles, and the results show degradation in the cell retention properties due to elemental segregation. The above experiments are enabled by the use of an on-chip fast heater and thermometer called as microthermal stage (MTS) integrated with a vertical phase change memory (PCM) cell. The temperature at the PCM layer can be controlled up to 600 K using MTS and with a thermal time constant of 800 ns, leading to heating rates ∼10(8) K/s that are close to the typical device operating conditions during PCM programming. The MTS allows us to independently control the electrical and thermal aspects of phase transformation (inseparable in a conventional PCM cell) and extract the temperature dependence of key material properties in real PCM devices.


Nano Letters | 2015

Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier.

Chiyui Ahn; Scott W. Fong; Yong-Sung Kim; Seunghyun Lee; Aditya Sood; Christopher M. Neumann; Mehdi Asheghi; Kenneth E. Goodson; Eric Pop; H.-S.P. Wong

Phase-change memory (PCM) is an important class of data storage, yet lowering the programming current of individual devices is known to be a significant challenge. Here we improve the energy-efficiency of PCM by placing a graphene layer at the interface between the phase-change material, Ge2Sb2Te5 (GST), and the bottom electrode (W) heater. Graphene-PCM (G-PCM) devices have ∼40% lower RESET current compared to control devices without the graphene. This is attributed to the graphene as an added interfacial thermal resistance which helps confine the generated heat inside the active PCM volume. The G-PCM achieves programming up to 10(5) cycles, and the graphene could further enhance the PCM endurance by limiting atomic migration or material segregation at the bottom electrode interface.


Physical Review Letters | 2016

Picosecond Electric-Field-Induced Threshold Switching in Phase-Change Materials

Peter Zalden; Michael J. Shu; Frank Chen; Xiaoxi Wu; Yi Zhu; Haidan Wen; Scott Johnston; Zhi-Xun Shen; Patrick Landreman; Mark L. Brongersma; Scott W. Fong; H.-S. Philip Wong; Meng-Ju Sher; Peter Jost; Matthias Kaes; Martin Salinga; Alexander von Hoegen; Matthias Wuttig; Aaron M. Lindenberg

Many chalcogenide glasses undergo a breakdown in electronic resistance above a critical field strength. Known as threshold switching, this mechanism enables field-induced crystallization in emerging phase-change memory. Purely electronic as well as crystal nucleation assisted models have been employed to explain the electronic breakdown. Here, picosecond electric pulses are used to excite amorphous Ag_{4}In_{3}Sb_{67}Te_{26}. Field-dependent reversible changes in conductivity and pulse-driven crystallization are observed. The present results show that threshold switching can take place within the electric pulse on subpicosecond time scales-faster than crystals can nucleate. This supports purely electronic models of threshold switching and reveals potential applications as an ultrafast electronic switch.


Journal of Applied Physics | 2016

Thermal conductivity measurement of amorphous dielectric multilayers for phase-change memory power reduction

Scott W. Fong; Aditya Sood; L. Chen; Niru Kumari; Mehdi Asheghi; Kenneth E. Goodson; Gary Gibson; H.-S.P. Wong

In this work, we investigate the temperature-dependent thermal conductivities of few nanometer thick alternating stacks of amorphous dielectrics, specifically SiO2/Al2O3 and SiO2/Si3N4. Experiments using steady-state Joule-heating and electrical thermometry, while using a micro-miniature refrigerator over a wide temperature range (100–500 K), show that amorphous thin-film multilayer SiO2/Si3N4 and SiO2/Al2O3 exhibit through-plane room temperature effective thermal conductivities of about 1.14 and 0.48 W/(m × K), respectively. In the case of SiO2/Al2O3, the reduced conductivity is attributed to lowered film density (7.03 → 5.44 × 1028 m–3 for SiO2 and 10.2 → 8.27 × 1028 m–3 for Al2O3) caused by atomic layer deposition of thin-films as well as a small, finite, and repeating thermal boundary resistance (TBR) of 1.5 m2 K/GW between dielectric layers. Molecular dynamics simulations reveal that vibrational mismatch between amorphous oxide layers is small, and that the TBR between layers is largely due to imperf...


IEEE Transactions on Electron Devices | 2017

Phase-Change Memory—Towards a Storage-Class Memory

Scott W. Fong; Christopher M. Neumann; H.-S. Philip Wong

Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade.


international memory workshop | 2017

Dual-Layer Dielectric Stack for Thermally-Isolated Low-Power Phase-Change Memory

Scott W. Fong; Chris M. Neumann; H.-S. Philip Wong

Thermal confinement has been used to reduce the reset energy of phase-change memory (PCM) devices and prevent heat losses into the surrounding structure. Specifically, for confined PCM cells, most of the heat losses were found to be into the surrounding dielectric. This work explores reset energy reduction attained by implementing a dual-layer dielectric stack as the dielectric in PCM devices to reduce heat loss to the surrounding dielectric. Reset energies of 69 &#177; 11 pJ and reset currents of 190 &#177; 13 &#x00B5;A are attained for a 500 nm &#x000D7; 20 nm heater contact area. Compared to SiO2 devices of identical dimensions, this shows a 44% current reduction and 54% energy reduction enabled with this simple modification of the fabrication process. Finite-element simulation results show that the energy reduction is primarily caused by improved heating of the phase-change layer and reduced heat loss into the dielectric.


Archive | 2017

Synaptic Devices Based on Phase-Change Memory

Yuhan Shi; Scott W. Fong; H.-S. Philip Wong; Duygu Kuzum

The biological brain has the capability of learning, pattern recognition, processing imprecisely defined data, and executing complex computational tasks. Consisting of 1011 neurons and 1015 synapses as the major computational components, the biological brain is extremely power efficient, massively parallel, structurally plastic, and exceptionally robust against noise and variations (Kuzum et al. Nanotechnology 24:382001, 2013). The question of how to design and build a compact neuromorphic system is a grand challenge for academia and industry. An electronic synaptic device is an essential element in such neuromorphic systems. Among various electronic synapses candidates, nonvolatile memory-based synaptic devices have the highest potential to realize massive parallelism and 3D integration for achieving high function per unit volume. This chapter will focus on synaptic devices based on phase-change memory (PCM). We first review the basics of phase-change synaptic devices: device operation, phase-change materials, conduction mechanism, power consumption, and scaling. We then review the use of PCM synaptic device implementations spanning from single device operation to various array architecture designs in the following sections. The concept of spike-timing-dependent plasticity (STDP), various pulse scheme designs, and pulse programming techniques for plasticity will be explained and compared. Last, we will discuss recent advances in designing PCM synaptic device to achieve lower power consumption and more stable resistance states.


international electron devices meeting | 2016

Microsecond transient thermal behavior of HfOx-based resistive random access memory using a micro thermal stage (MTS)

Zizhen Jiang; Ziwen Wang; Xin Zheng; Scott W. Fong; Shengjun Qin; Hong-Yu Chen; Chiyui Ahn; Ji Cao; Yoshio Nishi; H.-S. Philip Wong

Microsecond transient thermal disturbance (TD) on the conduction and switching of HfOX-based resistive random access memory (RRAM) is investigated using a micro thermal stage (MTS). Temperature-dependent measurement (298–1134 K) induced from MTS is applied to the RRAM during forming, read, write, and reliability measurements for DC and AC conditions. The temperature of the conductive filament (CF) that was inferred from ex-situ TEM observation of the crystallization is > 850 K in [1]. In this work, the time scale of the temperature-dependent measurement is extended from DC down to ∼ 10 μs. The contributions of various mechanisms (drift, Soret and Fick diffusion) of the oxygen ion migration are analyzed using MTS-induced heating. Electric field assisted oxygen ion migration is shown to be the dominant switching mechanism for fast AC switching (pulse width 100 ns with the ambient temperature 298–1047 K). During the fast SET and RESET process (100 ns) at 300–600 K, Soret diffusion (due to the temperature gradient) is stronger and enlarges CF while Fick diffusion (due to the concentration gradient) is not noticeable. Above 400–600 K, Fick force overrides Soret force, driving the resistance to a higher value. A compact model is developed to capture the physics, and TD on the array performance is estimated. In the middle layer (16th) of a 3D array (64 × 64 × 32), 20 % of the cells will be programmed with a resistance shift due to local temperature rise, and as a result 2.2% write failure may occur due to the TD caused by the previous programming cycle.


intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2014

Characterization of phase-change layer thermal properties using a micro-thermal stage

Scott W. Fong; Rakesh Jeyasingh; Mehdi Asheghi; Kenneth E. Goodson; H.-S.P. Wong

Recent progress using a micro-thermal stage (MTS) allowed the control the temperature of microstructures with sub-μs time scales. This approach was applied to phase-change memory (PCM) cells to measure thermal material and device properties. In this work, we use the change in MTS thermal resistance to predict changes in the thermal conductivity or thickness of the nearby phase-change layer (PCL). More generally, we show that the MTS can be placed in-situ of a complicated system to measure the thermal properties of a single changing layer. Electrical measurements of the MTS are performed on several different structures with different PCL thicknesses including 35, 70, and 100 nm thick Ge2Sb2Te5 (GST) films, a different phase-change material, and no PCL. Simulations establish the expected relationship between the MTS temperature for different input PCL thermal properties. The simulation approach is then scaled to match the experimental data and predicts the temperature in the PCL for different PCL thermal properties. Additionally, an analytical thermal circuit model is developed to describe the thermal profile of the system. The calibrated simulation and analytical models are thus able to determine thermal properties of the buried PCL by making purely electrical measurements of the MTS.

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Mark L. Brongersma

Geballe Laboratory for Advanced Materials

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