Sean C. O'Brien

65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features

Among the valid gate pattern strategies for the 65nm technology node, att-PSM offers the advantage in cost and mask complexity over other contenders such as complimentary alt-PSM and chromeless phase lithography (CPL). A combination of Quasar illumination and sub-resolution assist features (SRAFs) provides a through pitch solution with a common depth of focus (DOF) better than 0.25um to support the aggressive scaling in both logic and high density SRAM. A global mask-source optimization scheme is adopted to explore the multi-dimensional space of process parameters and define the best overall solution that includes scanner optics such as NA and illumination, and SRAF placement rules for 1-dimensional line and space patterns through the full pitch range. Gate pattern capabilities in terms of DOF, exposure latitude, mask error enhancement factor (MEEF), optical proximity correction (OPC), CD control, and aberration sensitivity are reported in this paper. Conflict resolution and placement optimization are key to the success of implementation of SRAF to the complex 2-dimensional layouts of random logic. Reasonable CD control can be achieved based on the characterization and simulation of CD variations at different spatial and processing domains from local to across chip, across wafer, wafer-to-wafer, and lot-to-lot. Certain layout restrictions are needed for high performance devices which require a much tighter gate CD distribution. Scanner optimization and enhancement such as DoseMapper are key enablers for such aggressive CD control. The benefits, challenges, and possible extensions of this particular approach are discussed in comparison with other techniques.

Immersion effects on lithography system performance

The immersion effects on lithography-system performance have been investigated using a ASML TWINSCAN XT:1250Di immersion-ArF scanner (NA=0.85) and Tokyo Electron CLEAN TRACK ACT12 at IMEC. Effects of immersion-induced-temperature change and effects of material-top surface are discussed in this paper. The wafer-stage temperature is measured during the leveling-verification tests and compared with the observed residual-focus-error change. The results indicate that stage-temperature change under an immersion environment can induce a focus change. In this paper, it was proved that the improved-temperature-control stage is effective to mitigate the immersion-specific focus change. The immersion effect on overlay is also investigated as a function of material top surface. It was demonstrated that the effect of material-receding-contact angles on the grid-residual errors (non-correctable errors) is small in the latest-immersion-hardware configuration of the scanner. However, there was a tendency that material with a smaller-receding-contact angle has a larger-wafer scaling although it is a correctable parameter. This can be caused by the first-layer wafer shrinkage due to more water evaporation on the more-hydrophilic surface. The immersion effect on scanner-dynamic performance is then investigated by changing the material-top surface and the scan speed of the scanner. It was turned out that the scan synchronization is not much affected by differences of material receding-contact-angles for the new configuration of the scanner. Moving-standard deviation of the synchronization error in scanning direction (y-direction) is slightly more affected by increased scanning speed, although it stays within specification even at a maximum scan speed of 500 mm/sec. Finally the immersion effects on resist-profile uniformity are examined. It was found that lower-leaching-film stacks (with a top coat or a lower leaching resist) seem to mitigate the variation of resist-profile uniformity.

Design rule considerations for 65-nm node contact using off axis illumination

Perhaps the most critical lithographic challenge at teh 65 nm node can be found printing contact holes for random logic. Achieving all pitches from dense to isolated simultaneously in a single mask print requires high numerical aperture (NA) with novel low-k1 imaging techniques. As is typical in complex engineering problems, requirements compete against each other. The requirement to achieve the desired dense resolution suggests the use of off axis illumination (OAI) techniques such annular and Quasar. At the same time, the need to meet other figures of merit (FOM) such as depth of focus (DOF) and mask error enhancement factor (MEEF) for larger pitches are strong considerations for choosing the more conventional illumination conditions. Moreover, previously unconsidered FOMs such as contact asymmetry and displacement must now also be strongly considered. In particular, we discuss design limitations which may be incorporated to avoid fundamental patterning issues when using OAI and sub-resolution assist features (SRAF) for printing CT level at 65 nm node.

Exposure latitude requirements for high yield with photon flux-limited laser sources

This paper presents an analysis of quantum statistical limits on photolithographic imaging of very large arrays of semiconductor features. In flux limited imaging systems the photon counting statistics contribute to the overall process variation. There is a direct relationship between exposure latitude and sensitivity to photon counting statistics. For example, in an array of 1 million 90 nm contact holes imaged with 20 mJ/cm2 of 157 nm light 1350 of these holes will receive a total dose less than 98% of the mean dose. If the exposure latitude is 4% then these 1350 contacts will print out-of-spec as a result of the Poisson statistical distribution of photon-limited light sources (sometimes called shot-noise). High yield for volume semiconductor manufacturing requires failure rates well below this level. Each new device generation requires more functional transistors than the previous one, increasing approximately linearly. As the imaging wavelength decreases the net number of photons available decreases linearly (assuming constant laser power). The area of a contact hole decreases as the square of the critical dimension. Thus the fraction of chips with at least one contact hole receiving inadequate dose increases approximately as the fourth power of the wavelength. This presents serious implications for 157nm lithography semiconductor yield. Electron imaging systems are not immune to this either, Poisson limited intensity uniformity is nearly identical with that of optical imaging. 157 nm lithography is marginal to photon-statistics limited yield, and 13 nm EUV lithography yield is almost certainly photon limited. In addition, as transistor array size increases the 0.987 ppb failure rate of a 6-sigma process will not be sufficient for high yield. Thus 8 or 9-sigma processing will be needed along with significant improvement in exposure latitude and optimized resist sensitivity will be necessary.

Rules based process window OPC

As a preliminary step towards Model-Based Process Window OPC we have analyzed the impact of correcting post-OPC layouts using rules based methods. Image processing on the Brion Tachyon was used to identify sites where the OPC model/recipe failed to generate an acceptable solution. A set of rules for 65nm active and poly were generated by classifying these failure sites. The rules were based upon segment runlengths, figure spaces, and adjacent figure widths. 2.1 million sites for active were corrected in a small chip (comparing the pre and post rules based operations), and 59 million were found at poly. Tachyon analysis of the final reticle layout found weak margin sites distinct from those sites repaired by rules-based corrections. For the active layer more than 75% of the sites corrected by rules would have printed without a defect indicating that most rulesbased cleanups degrade the lithographic pattern. Some sites were missed by the rules based cleanups due to either bugs in the DRC software or gaps in the rules table. In the end dramatic changes to the reticle prevented catastrophic lithography errors, but this method is far too blunt. A more subtle model-based procedure is needed changing only those sites which have unsatisfactory lithographic margin.

Improving asymmetric printing and low margin using custom illumination for contact hole lithography

Perhaps the most challenging level to print moving beyond 65 nm node for logic devices is contact hole. Achieving dense to isolated pitches simultaneously in a single mask print requires high NA with novel low-k1 imaging techniques. In order to achieve the desired dense resolution, off axis illumination (OAI) techniques such as annular and quasar are necessary. This also requires incorporation of sub-resolution assist features for improved semidense to isolated contact margin. We have previously discussed design related issues revolving around asymmetric contact hole printing and misplacement associated with using extreme off axis illumination (OAI). While these techniques offer the appropriate dense margin needed, there are regions of severe asymmetric printing which are unsolvable using optical proximity correction (OPC). These regions are impossible to avoid unless design rule restrictions or new illumination schemes are implemented. We continue this work with discussions revolved around illumination choices for alleviating these regions without losing too much dense margin.

Study of integration issues in shallow trench isolation for deep submicron CMOS technologies

This paper presents a study of the issues in integrating the pattern, fill, planarization and surface cleanup processes to design a shallow trench isolation (STI) flow suitable for 0.25 micrometers CMOS technologies. Technological choices and their effects on the characteristics of the STI technology are discussed. Experimental data is presented to illustrate how process choices at various stages of the STI flow are made to optimize the STI structure.