Mark Terry

Behavior of lens aberrations as a function of wavelength on KrF and ArF lithography scanners

In this paper we study the effects of changing the operating laser wavelength on the projection lens aberrations of KrF and ArF scanners as measured by the Litel In-Situ Interferometer. Specifically, we quantify the change in 28 individual Zernike coefficients as a function of wavelength as well as the total RMS. Effects on Zernikes exhibiting a field dependent behavior are described in detail. We convert the Z4 terms to Z positions to estimate the displacement of the image plane, and we identify a new chromatic distortion term. Finally, we input the measured wavefronts into a lithographic simulator to estimate the full effects on image placement error.

65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features

Among the valid gate pattern strategies for the 65nm technology node, att-PSM offers the advantage in cost and mask complexity over other contenders such as complimentary alt-PSM and chromeless phase lithography (CPL). A combination of Quasar illumination and sub-resolution assist features (SRAFs) provides a through pitch solution with a common depth of focus (DOF) better than 0.25um to support the aggressive scaling in both logic and high density SRAM. A global mask-source optimization scheme is adopted to explore the multi-dimensional space of process parameters and define the best overall solution that includes scanner optics such as NA and illumination, and SRAF placement rules for 1-dimensional line and space patterns through the full pitch range. Gate pattern capabilities in terms of DOF, exposure latitude, mask error enhancement factor (MEEF), optical proximity correction (OPC), CD control, and aberration sensitivity are reported in this paper. Conflict resolution and placement optimization are key to the success of implementation of SRAF to the complex 2-dimensional layouts of random logic. Reasonable CD control can be achieved based on the characterization and simulation of CD variations at different spatial and processing domains from local to across chip, across wafer, wafer-to-wafer, and lot-to-lot. Certain layout restrictions are needed for high performance devices which require a much tighter gate CD distribution. Scanner optimization and enhancement such as DoseMapper are key enablers for such aggressive CD control. The benefits, challenges, and possible extensions of this particular approach are discussed in comparison with other techniques.

Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a number of questions that arise in such simulations. These questions include identification of stress effects causing context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin determination.

Design rule considerations for 65-nm node contact using off axis illumination

Perhaps the most critical lithographic challenge at teh 65 nm node can be found printing contact holes for random logic. Achieving all pitches from dense to isolated simultaneously in a single mask print requires high numerical aperture (NA) with novel low-k1 imaging techniques. As is typical in complex engineering problems, requirements compete against each other. The requirement to achieve the desired dense resolution suggests the use of off axis illumination (OAI) techniques such annular and Quasar. At the same time, the need to meet other figures of merit (FOM) such as depth of focus (DOF) and mask error enhancement factor (MEEF) for larger pitches are strong considerations for choosing the more conventional illumination conditions. Moreover, previously unconsidered FOMs such as contact asymmetry and displacement must now also be strongly considered. In particular, we discuss design limitations which may be incorporated to avoid fundamental patterning issues when using OAI and sub-resolution assist features (SRAF) for printing CT level at 65 nm node.

Context analysis and validation of lithography induced systematic variations in 65nm designs

The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI 65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours. Using model-based litho and etch simulation at different process conditions, contours were generated for the poly and active layers of standard cells in multiple contexts. Next, the extracted transistor-level SPICE netlists (with annotated changes in CD) were simulated for cell delay and leakage. The silicon contours predicted by the model-based litho tools were validated by comparing CDs of the simulated contours with SEM images. A comparative analysis of standard cells with relaxed design rules and restricted pitch design rules showed that restrictive design rules help reduce the variation from instance to instance of a given cell by as much as 15%, but at the expense of an area penalty. A full-chip variability analysis flow, including model-based lithography and etch simulation, captures the systematic variability effects on timing-critical paths and cells and allows for comparison of the variability of different cells and paths in the context of a real design.

Improving asymmetric printing and low margin using custom illumination for contact hole lithography

Perhaps the most challenging level to print moving beyond 65 nm node for logic devices is contact hole. Achieving dense to isolated pitches simultaneously in a single mask print requires high NA with novel low-k1 imaging techniques. In order to achieve the desired dense resolution, off axis illumination (OAI) techniques such as annular and quasar are necessary. This also requires incorporation of sub-resolution assist features for improved semidense to isolated contact margin. We have previously discussed design related issues revolving around asymmetric contact hole printing and misplacement associated with using extreme off axis illumination (OAI). While these techniques offer the appropriate dense margin needed, there are regions of severe asymmetric printing which are unsolvable using optical proximity correction (OPC). These regions are impossible to avoid unless design rule restrictions or new illumination schemes are implemented. We continue this work with discussions revolved around illumination choices for alleviating these regions without losing too much dense margin.

DFM aware bridge pair extraction for manufacturing test development

We propose a novel method to extract bridge pairs for manufacturing test development based on litho hotspots obtained from DFM (Design-For-Manufacturability) litho models. Litho hotspots are locations in a physical layout in which the lithography process margin is relatively small. We use a DFM lithography simulator to identify litho hotspots and map them onto the design database to identify the associated nets. These nets are then used to select prioritized bridging pairs from extracted capacitive coupling based bridge pairs.