Mark E. Mason

A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond

A manufacturable shallow trench isolation (STI) technology using high density plasma (HDP) CVD oxide as trench filling material is reported for the first time, and compared to using sub-atmospheric CVD (SACVD) oxide as filling material. HDP filled STI has excellent immunity to double-hump, better gate oxide integrity and inverse narrow width effect, due to its lower deglaze rate and thus better corner protection compared to the SACVD case. The /spl Delta/Vt (between W=10 and 0.18 /spl mu/m) are 150 mV (NMOS). And 60 mV (PMOS) for the HDP case, and the transistor width reduction is /spl les/0.03 /spl mu/m for both cases. Trench wall passivation and a low sputtering component during deposition are necessary for HDP to achieve low diode edge leakage. 0.28 /spl mu/m intra-well isolation (or 0.46 /spl mu/m min. pitch), 0.6 /spl mu/m n/sup +/-to-p/sup +/ isolation, latch-up holding voltage of 2 V at 0.5 /spl mu/m n/sup +/-to-p/sup +/ spacing, together with outstanding CMOS transistor and inverter performance, have been achieved. These results are either comparable to or better than the best results reported to date. It is concluded that HDP trench filling oxide is a viable approach, while SACVD oxide is marginally acceptable, for the STI of 0.25/0.18 /spl mu/m CMOS.

DFM EDA Technology: A Lithographic Perspective

Design for manufacturability (DFM) is a broadly used term that can be applied to many yield-related activities in the semiconductor industry. However, recent focus in the industry has centered on managing the impact of the increasing complexity of lithography on process and electrical yield. This paper looks at the evolution of DFM tools with a focus on the impact of lithography on design and how electronic design automation (EDA) tools will be used to compensate for the increasing difference between ideal design data and resulting structures on silicon wafers.

65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features

Among the valid gate pattern strategies for the 65nm technology node, att-PSM offers the advantage in cost and mask complexity over other contenders such as complimentary alt-PSM and chromeless phase lithography (CPL). A combination of Quasar illumination and sub-resolution assist features (SRAFs) provides a through pitch solution with a common depth of focus (DOF) better than 0.25um to support the aggressive scaling in both logic and high density SRAM. A global mask-source optimization scheme is adopted to explore the multi-dimensional space of process parameters and define the best overall solution that includes scanner optics such as NA and illumination, and SRAF placement rules for 1-dimensional line and space patterns through the full pitch range. Gate pattern capabilities in terms of DOF, exposure latitude, mask error enhancement factor (MEEF), optical proximity correction (OPC), CD control, and aberration sensitivity are reported in this paper. Conflict resolution and placement optimization are key to the success of implementation of SRAF to the complex 2-dimensional layouts of random logic. Reasonable CD control can be achieved based on the characterization and simulation of CD variations at different spatial and processing domains from local to across chip, across wafer, wafer-to-wafer, and lot-to-lot. Certain layout restrictions are needed for high performance devices which require a much tighter gate CD distribution. Scanner optimization and enhancement such as DoseMapper are key enablers for such aggressive CD control. The benefits, challenges, and possible extensions of this particular approach are discussed in comparison with other techniques.

Mechanical distortions in advanced optical reticles

Finite element models have been developed and refined to simulate the mechanical distortions associated with mask blank fabrication, pattern transfer, and exposure clamping. By modeling the substrate with layers associated with the mask fabrication process and then by prestressing specified layers, the resulting out-of-plane and in-plane distortions of the mask blank have been determined. Etching procedures were subsequently simulated to assess the pattern transfer distortions associated with both dark and bright field masks. Investigations included substrate materials which have acceptable optical transmission for wavelengths below 180 nm. Additional mechanical distortions associated with clamping the reticle into the exposure mount have also been considered.

Design enablement: The challenge of being early, accurate, and complete

Progress evidenced by Moores Law has driven increased performance at decreased cost per function. Often, the price of this progress is balanced against complexity and time-to-market (both directly impacting cost). Design enablement teams must mitigate these cost factors by delivering accurate process design kits (PDKs) that predict both process and device performance at production on a schedule that supports time-to-market goals. Here, we examine some key technology issues affecting the critical relationship between process, device, design and products.

The rising cost and complexity of RETs

For the last several years, Resolution Enhancement Technologies (RETs) have helped make it possible for lithographers to stay on the path set for them by Goordon Moore. Though seldom discussed in detail, these RETs have a real cost in terms of data file size, computation times, complexity of metrology and inspection, licenses fees, manpower and delay. The International Sematech Cost of Ownership (CoO) analysis can be used to estimate the impact of RETs on overall Lithography CoO and on the cost per modern semiconductor wafer, which appears to be around

Influence of film stress on advanced optical reticle distortions

10/ RET level for a high-volume ASIC case.

Mask design rules (45 nm) : Time for standardization

As optical lithography error budgets on pattern placement become more and more stringent for sub-130 nm technology, all mask-related distortions must be quantified, controlled, and minimized. To optimize the mask fabrication process, it is essential to identify the stress magnitudes of the thin films and determine the resulting effect on pattern placement errors. Experiments utilizing surface mapping technique have been used to quantify the stress magnitudes of current thin film deposition parameters used in photomask blank fabrication. The effect of pattern transfer on image placement errors was determined experimentally for an anisotropic metrology pattern. The stress magnitudes obtained in the thin film stress measurements were incorporated into a finite element model that simulated the mechanical effect of pattern transfer utilizing equivalent modeling techniques. Analytical, experimental, and finite element procedures have been integrated to accurately quantify thin film stress magnitudes and the corresponding pattern transfer distortions.

Design rule considerations for 65-nm node contact using off axis illumination

Time-to-mask (ttm) has been growing exponentially in the subwavelength era with the increased application of advanced RETs (Resolution Enhancement Technology). Not only are a greater number of design/mask layers impacted but more-and-more layers also have more severe restrictions on critical dimension uniformity (CDU) despite operating at a very low k1 factors necessitating rigorous but practical tolerancing. Furthermore, designs are also more complex, may be built up from blocks spanning different design styles, and occupy increasingly-large Rayleigh field areas. Given these factors and scales, its no wonder that the cycle time for verification of a design following RET, is growing however it is doing so exponentially and that this is a critical factor impeding ttm. Until an unambiguously interprable and standard Mask Design Rule (MaskDR) set is created, neither the designer nor the mask supplier can reliably verify manufacturability of the mask for the simple reason that ambiguity and inter-rule conflict are at the source of the problem and that the problem increasingly requires cooperation spanning a large ecosystem of tool, IP, and mask suppliers all needing to essentially speak the same language. Since the 130 nm node, Texas Instruments has enforced a strict set of mask rule checks (MRCs) in their mask data preparation (MDP) flow based on MaskDRs negotiated with their mask suppliers. The purpose of this effort has been to provide an a-priori guarantee that the data shipped to the mask shop can be used to manufacture a mask reliably and with high yield both from a mask standpoint and from the silicon standpoint. As has been reported earlier, mask manufacturing rules are usually determined from assumed or experimentally acquired/validated mask-manufacturing limits. These rules are then applied during RET/MDP data treatment to guide and/or limit pattern correction strategies. With increasing RET and low-k1 lithography challenges, the importance of MRCs compounds. Furthermore, it will be necessary to comprehend certain MRC restrictions in the design flow as well as in the RET and MDP space. While mask tool manufacturers will need to be able specify tools specifications relevant to the MRCs for a particular mask shop flow, software tool suppliers, such as for RET, need to do so as well with tools which comprehend, check for, and enforce MRCs consistently. IDMs, foundaries, mask shops, EDA companies and tool suppliers will need a common language for the discussion on MaskDRs and MRCs in order to reach unambiguous convergence. Experience at Texas Instruments shows that accurate description, specification, and interpretation of MaskDRs and applying the associated MRCs is critical to a successful advanced mask technology strategy. This paper proposes the creation of a standard MaskDR lexicon. The goal of such a lexicon is the standardization of MaskDRs and their definitions such that interested parties from various mask-related disciplines can discuss, negotiate, specify, test and enforce MaskDRs unambiguously. We further propose that this standard be machine readable and directly usable without the necessity for intermediate interpretations. This lexicon would allow the designers, IDMs, foundaries, mask suppliers, and equipment suppliers to unambiguously negotiate and agree upon mask manufacturability requirements for their particular application.

Exposure latitude requirements for high yield with photon flux-limited laser sources

Perhaps the most critical lithographic challenge at teh 65 nm node can be found printing contact holes for random logic. Achieving all pitches from dense to isolated simultaneously in a single mask print requires high numerical aperture (NA) with novel low-k1 imaging techniques. As is typical in complex engineering problems, requirements compete against each other. The requirement to achieve the desired dense resolution suggests the use of off axis illumination (OAI) techniques such annular and Quasar. At the same time, the need to meet other figures of merit (FOM) such as depth of focus (DOF) and mask error enhancement factor (MEEF) for larger pitches are strong considerations for choosing the more conventional illumination conditions. Moreover, previously unconsidered FOMs such as contact asymmetry and displacement must now also be strongly considered. In particular, we discuss design limitations which may be incorporated to avoid fundamental patterning issues when using OAI and sub-resolution assist features (SRAF) for printing CT level at 65 nm node.