Scott William Jessen

Across wafer focus mapping and its applications in advanced technology nodes

The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact the device yield. A technique based on the Phase-Shift Focus Monitor (PSFM) is developed to measure realistic across-wafer focus errors on materials processed in actual production flows. With this technique, we are able to extract detailed across-wafer focus performance at critical pattern levels from the front end of line (FEOL) all the way through the back end of line (BEOL). Typically, more than 8,000 data points are measured across a wafer, and the data are decomposed into an intra-field focus map, which captures the across chip focus variation (ACFV), and an inter-field focus map, which describes the across wafer focus variation (AWFV). ACFV and AWFV are then analyzed to understand various components in the overall focus error, including; across slit lens image field, reticle shape and dynamic scan components, local wafer flatness, wafer processing effect, pattern density, and edge die abnormality. The intra-field ACFV lens component is compared with TIs ScatterLith and ASMLs FOCAL techniques. Results are consistent with the predictions based on the on-board lens aberration data. Inter-field AWFV is the most interesting, due to lack of detailed understanding of the process impact on scanner focus and leveling. PSFM data is used to characterize the effect of wafer processing such as etch, deposition, and CMP on across wafer focus control. Comparison and correlation of PSFM focus mapping with the wafer height and residual moving average (MA) maps generated by the scanners optical leveling sensors shows a good match in general. Process induced focus errors are clearly observed on wafers of significant film stack variation and/or pattern density variation. Implications on total focus control and depth of focus (DOF) requirements for 65nm mass production are discussed in this paper using a quantitative pattern yield model. The same technique can be extended to immersion lithography.

Exploring complex 2D layouts for 22nm node using double patterning/double etch approach for trench levels

With the delay of a next-node lithography solution, lithographers are required to evaluate double patterning techniques such as double pattern/double etch (DP/DE) to meet scaling targets for the 22nm logic node. The tightest design rule level to pattern has traditionally been the first metal level. For this node, target minimum pitches are below 32 nm half pitch in order to meet cell area requirements. In this paper, we explore implications of the DP/DE approach when applied to complex 2D metal patterns. In addition to evaluating stitching rules for line ends, we move into complicated patterning structures such as landing pads neighboring metal runners and arrays of dense landing pads. These feature types are critical for area scaling; however, when these structures are patterned in a DP/DE scheme, the minimum area of the features needed for each pattern layer can be quite small. In this work, we explore minimum area rules for stitching together patterns as function of overlap with first pattern, minimum area and proximity to unrelated trench features on the same pattern. These results are shown thru simulation and on the wafer scale using a DP/DE approach which uses current 28 nm node imaging techniques.

Design rule considerations for 65-nm node contact using off axis illumination

Perhaps the most critical lithographic challenge at teh 65 nm node can be found printing contact holes for random logic. Achieving all pitches from dense to isolated simultaneously in a single mask print requires high numerical aperture (NA) with novel low-k1 imaging techniques. As is typical in complex engineering problems, requirements compete against each other. The requirement to achieve the desired dense resolution suggests the use of off axis illumination (OAI) techniques such annular and Quasar. At the same time, the need to meet other figures of merit (FOM) such as depth of focus (DOF) and mask error enhancement factor (MEEF) for larger pitches are strong considerations for choosing the more conventional illumination conditions. Moreover, previously unconsidered FOMs such as contact asymmetry and displacement must now also be strongly considered. In particular, we discuss design limitations which may be incorporated to avoid fundamental patterning issues when using OAI and sub-resolution assist features (SRAF) for printing CT level at 65 nm node.

Improving asymmetric printing and low margin using custom illumination for contact hole lithography

Perhaps the most challenging level to print moving beyond 65 nm node for logic devices is contact hole. Achieving dense to isolated pitches simultaneously in a single mask print requires high NA with novel low-k1 imaging techniques. In order to achieve the desired dense resolution, off axis illumination (OAI) techniques such as annular and quasar are necessary. This also requires incorporation of sub-resolution assist features for improved semidense to isolated contact margin. We have previously discussed design related issues revolving around asymmetric contact hole printing and misplacement associated with using extreme off axis illumination (OAI). While these techniques offer the appropriate dense margin needed, there are regions of severe asymmetric printing which are unsolvable using optical proximity correction (OPC). These regions are impossible to avoid unless design rule restrictions or new illumination schemes are implemented. We continue this work with discussions revolved around illumination choices for alleviating these regions without losing too much dense margin.

Improving 130nm node patterning using inverse lithography techniques for an analog process

Developing a new lithographic process routinely involves usage of lithographic toolsets and much engineering time to perform data analysis. Process transfers between fabs occur quite often. One of the key assumptions made is that lithographic settings are equivalent from one fab to another and that the transfer is fluid. In some cases, that is far from the truth. Differences in tools can change the proximity effect seen in low k1 imaging processes. If you use model based optical proximity correction (MBOPC), then a model built in one fab will not work under the same conditions at another fab. This results in many wafers being patterned to try and match a baseline response. Even if matching is achieved, there is no guarantee that optimal lithographic responses are met. In this paper, we discuss the approach used to transfer and develop new lithographic processes and define MBOPC builds for the new lithographic process in Fab B which was transferred from a similar lithographic process in Fab A. By using PROLITHTM simulations to match OPC models for each level, minimal downtime in wafer processing was observed. Source Mask Optimization (SMO) was also used to optimize lithographic processes using novel inverse lithography techniques (ILT) to simultaneously optimize mask bias, depth of focus (DOF), exposure latitude (EL) and mask error enhancement factor (MEEF) for critical designs for each level.

Mask challenges and capability development for the 65-nm device technology node: the first status report

The slow progress of the 157nm-F2 laser exposure tool development results in broad adaptation of high numerical aperture (NA>0.8) 193nm-ArF lithography for the 65nm-node production solution. This decision, however, forces lithographers to increase dependency on very aggressive RET technologies. This in turn demands mask making capabilities the industry has never faced before such as 100nm (@4X on mask scale) size Sub Resolution Assist Features (SRAF). This report covers our early work on our mask making capability development for the 65nm-node process technology development cycle for production in 2005. Our report includes the 65nm node mask technology capability development status for mask CD and registration dimensions control, current inspection capability/issues and development efforts for critical layer masks with aggressive RET (especially of EAPSM with SRAF).