Kazuaki Nakajima

Improvement of threshold voltage deviation in damascene metal gate transistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

Low-resistivity poly-metal gate electrode durable for high-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800/spl deg/C. The sheet resistivity of the W(100 nm)/WN/sub x/(5 nm)/poly-Si(100 nm) structure is as low as 1.5 /spl Omega//spl par//spl square/ and independent of line-width from 0.52 /spl mu/m to 0.12 /spl mu/m. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated.

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.

Double tunnel junctions for magnetic random access memory devices

Optimum junction resistance and minimum tunnel magnetoresistance (TMR) ratio required for high density and high performance magnetoresistive random access memory (MRAM) devices with a TMR cell plus field effect transistor (FET) switch architecture are discussed by taking into account the variation of FET resistance causing noise. This implies that a TMR ratio over 25% at a 400 mV bias voltage and junction resistance of several tens of kilo-ohms for TMR cells are required with a signal voltage of 30 mV and a sense current of 10 μA, which leads to about 10 ns read time. This large magnetoresistance ratio at the elevated bias voltage requires low bias voltage dependence of TMR for the MRAM devices. In order to try to meet this requirement, double tunnel junctions were fabricated which possess the central ferromagnetic layer consisting of a thin discontinuous layer of hard ferromagnetic Co80Pt20 nanoparticles and insulating Al2O3 prepared by alternate sputtering of Co80Pt20 and Al2O3 targets. The maximum TMR ...

Formation mechanism of ultrathin WSiN barrier layer in a W/WNx/Si system

Abstract A W/WN x /poly-Si composite structure (poly-metal) has been proposed as a low resistivity gate material. It has been found that an ultrathin WSiN layer forms at the W/Si interface after annealing, and as a result, the W/WSiN/poly-Si structure is very stable up to 950°C. In this paper, the formation mechanism of the ultrathin WSiN layer was studied. It was found that a 1 nm WSiN layer forms by solid state reaction between the WN x and poly-Si during annealing. A part of nitrogen atoms originally incorporated in the WN x film react with Si to form a 1 nm WSiN layer during annealing. Chemical bonds in the ultrathin WSiN layer consists of SiN bonds and metallic W bonds. Metallic W bonds are attributed to WW or WSi bonds. There is no WN bonds. Therefore, it is speculated that the WSiN consists of Si 3 N 4 and W or WSi x , and stabilizes the W/poly-Si interface. Since the WSiN layer acts as an excellent barrier metal for W and Si diffusion, the sheet resistivity of the poly-metal structure (where W thickness is 100 nm) can be maintained to be lower than 1.5 ω/sq.

Work function controlled metal gate electrode on ultrathin gate insulators

We investigated MOS characteristics of metal gate electrodes on ultrathin gate oxide. Gate leakage currents of sputtered TiN and WN/sub x/ electrodes were found to be much higher than that of CVD TiN electrodes due to metal penetration during sputtering. Moreover, the deviation of crystal orientation of the TiN was found to affect the flat band voltage. The CVD TiN film was found to be formed with highly preferred orientation and to show very stable MOS characteristics, even on 2 nm gate oxide.

W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

In this paper, a new gate structure, W/WNx/poly-Si, was proposed as the breakthrough to combat the serious parasitic effect caused by RC delay of gate electrode in down-scaled CMOS devices. MOSFETs with the gate electrode structure were fabricated with a deep submicron CMOS process. As a result, 1.6/spl Omega//spl square/ gate sheet resistance without an increase in fine line gate was obtained. Moreover, it was demonstrated that the thin WNx layer formed by reactive sputtering can be an excellent barrier layer from the gate oxide integrity and W/poly-Si contact resistivity point of view.<<ETX>>

Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond

Integration technology of low resistance word line and scaled CMOSFETs for 1 Gbit DRAMs and beyond is proposed. Polymetal (W/WSiN/Poly-Si) word lines and dual gate CMOS FETs with oxynitride gate dielectric were introduced to the 8F/sup 2/ DRAM cell technology. Low sheet resistance of 4.5 /spl Omega///spl square/ word line with 40 nm thick W and high performance dual gate 0.18 /spl mu/m CMOS were successfully integrated without any constraint.

Reduction of threshold voltage deviation in Damascene metal gate MOSFETs

The Damascene metal gate transistors are found to exhibit characteristics superior to those of the conventional polysilicon gate transistors with respect to the threshold voltage deviation (/spl Delta/V/sub th/) and the subthreshold swing (S-factor) when the metal gate work function deviation (crystal orientation deviation) is suppressed by using the inorganic CVD technique. The mechanisms of the gate length dependence of /spl Delta/V/sub th/ and S-factor in the Damascene metal gate transistors can be explained by metal gate work function deviation in the channel region.

Silicon-Based Single-Electron-Tunneling Transistor Operated at 4.2 K

We have fabricated single-electron-tunneling transistors using silicon which is a useful material for device applications. The device is composed of thin polycrystalline silicon film patterned by electron-beam lithography and its thermally grown oxidized film. We have observed, in this device, periodic conductance oscillations as a function of gate voltage and nonlinear resistances as a function of drain voltage at 4.2 K. These experimental results are in agreement with the theory of Coulomb blockade. We conclude that the observed behavior results from the charging energy of single-electron tunneling.