Tomohiro Saito

High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regime

We propose a plasma and thermal damage-free gate process named the Damascene gate process where CMP (Chemical Mechanical Polishing) is used in forming the gate structure. By using this process, fully planarized high performance metal (W/TiN or Al/TiN) gate transistors with pure SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were fabricated with very uniform and highly reliable electrical characteristics. Therefore, this technology is useful in fabricating 0.1 /spl mu/m MOSFETs and beyond.

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

We propose an IBA scheme based on a pull-out detection, which is suitable for implementing in a circuit. The scheme is implemented in a driver IC that is part of a module with an RF MEMS variable capacitor. No failures are observed over 108 cycles at 85degC, which is an accelerated charging condition.

A high power-handling RF MEMS tunable capacitor using quadruple series capacitor structure

This paper presents an RF MEMS tunable capacitor that achieves an excellent power-handling property with relatively low actuation voltage. The tunable capacitor consists of two fixed MIM (Metal-Insulator-Metal) capacitors and two MEMS capacitor elements, all connected in series. This quadruple series capacitor (QSC) structure enables reduction of the actuation voltage without sacrificing the power-handling capability, since the MIM capacitor reduces the RF voltage amplitude applied to the MEMS capacitors. The measured result demonstrates +36dBm hot-switching at 85°C with 21V pull-in voltage.

Improvement of threshold voltage roll-off by ultra-shallow junction formed by flash lamp annealing

Flash lamp annealing (FLA) was first applied to complementary MOSFETs (CMOS) as a new method of activating implanted impurities in source and drain. By optimizing ion implantation and activation annealing conditions, junction depth less than 10 nm with good junction leakage were successfully obtained for both p/sup +//n and n/sup +//p junctions. Threshold voltage (V/sub th/) roll-off characteristics for MOSFETs fabricated by FLA show drastic improvement as compared with conventional spike annealing.

Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current, and uniform electrical characteristics

We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (0.7 V). By using this technology, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with mid-gap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V).

Conformable formation of high quality ultra-thin amorphous Ta/sub 2/O/sub 5/ gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFETs

A conformable formation process of ultra-thin Ta/sub 2/O/sub 5/ gate dielectrics, which is applicable to 50 nm damascene gate MOSFETs, was developed. Assisted by H/sub 2/O, perfect conformability was successfully realized even in the narrow gate groove (50 nm), while maintaining a low gate leakage. An excellent device performance of S-factor 72 mV/decade was obtained in 90 nm MOSFET with amorphous Ta/sub 2/O/sub 5/ gate dielectrics of T/sub eff/ 1.6 nm.

Reduction of threshold voltage deviation in Damascene metal gate MOSFETs

The Damascene metal gate transistors are found to exhibit characteristics superior to those of the conventional polysilicon gate transistors with respect to the threshold voltage deviation (/spl Delta/V/sub th/) and the subthreshold swing (S-factor) when the metal gate work function deviation (crystal orientation deviation) is suppressed by using the inorganic CVD technique. The mechanisms of the gate length dependence of /spl Delta/V/sub th/ and S-factor in the Damascene metal gate transistors can be explained by metal gate work function deviation in the channel region.

Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation of under 0.7 V

We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (under 0.7 V). In this technology the metal gate is formed by the damascene gate process and directly connected to the well region (Si-body). Therefore, the connection between gate electrode and silicon body can be more easily fabricated in the DT-DMG transistor than with conventional technologies. Furthermore, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with midgap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V).

Low profile double resonance frequency tunable antenna using RF MEMS variable capacitor for digital terrestrial broadcasting reception

It is difficult to realize the built-in antenna for wideband systems, because a frequency bandwidth of the low profile antenna is narrow. A frequency tunable antenna is a technique for wideband characteristics. In this paper a low profile double resonance frequency tunable antenna using MEMS variable capacitors is presented. It has high efficiency over a wide frequency band. Through both resonant portions from 465 to 665 MHz, the efficiency of more than −4 dB and the VSWR of less than 3 are observed in the measurement using the variable capacitor of 0.4–0.9 pF.

High performance damascene gate CMOSFETs with recessed channel formed by plasma oxidation and etching method (RC-POEM)

We report on high performance transistors using a new recessed channel formed by plasma oxidation and etching method (RC-POEM). The advantages of RC-POEM are: [a] lowering source/drain extension sheet resistance while suppressing lateral diffusion of extension region; [b] forming pseudo-raised extension using only plasma oxidation and wet etching. RC-POEM suppressed short channel effects down to 35nm physical gate length and high drive current were obtained.