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Dive into the research topics where Seiji Yasuda is active.

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Featured researches published by Seiji Yasuda.


Solid-state Electronics | 1982

High-voltage planar junction with a field-limiting ring

Seiji Yasuda; Toshio Yonezawa

Abstract A twodimensional Poisson equation is solved as part of a program to improve breakdown characteristics of a planar p-n junction by using a field limiting ring. The influences of n− concentration and n− layer width of p+-n−-n+ diode are investigated. Higher n− concentration and smaller n− width make optimum distance between anode and field limiting ring smaller. Breakdown voltages predicted by optimising method reported agree well with the experimental results.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1989

Discretization problem for multidimensional current flow

Naoyuki Shigyo; Tetsunori Wada; Seiji Yasuda

An examination is made of discretization methods for the two-dimensional current continuity equation used in device simulation. The authors have introduced the Baliga-Patankar discretization scheme to a device simulator for the first time and compared this scheme with the popular Scharfetter-Gummel scheme by using silicon n/sup +/-p diode current-voltage characteristics. Test computation reveals that the two schemes result in a 16% difference in the current values for 1.5 V of forward bias and a two-dimensional n/sup +/-p diode structure. The Baliga-Patankar scheme is rather insensitive to mesh, compared with the Scharfetter-Gummel scheme. On the other hand, the two schemes result in the same current-voltage characteristics for a one-dimensional diode structure. These results originate from the one-dimensional nature of the Scharfetter-Gummel scheme for drift dominant flow. The Baliga-Patankar scheme is robust for the two-dimensional current flow case, since this scheme defines a current density vector within each element. >


Solid-state Electronics | 1990

Minority carrier mobility model for device simulation

Naoyuki Shigyo; M. Norishima; Seiji Yasuda

Abstract We present a new mobility model which incorporates a minority carrier mobility, for semiconductor device simulation. Mobility model used in device simulators is traditionally a function of the total impurity concentration. However, the proposed model is not a function of the total impurity concentration. This new model is implemented in a triangular-mesh device simulator, TRIMEDES. Simulated BJT current-voltage characteristics using the proposed model reveal excellent agreement with measurement.


Solid-state Electronics | 1980

Two-dimensional field distribution analysis of reverse biased p-n junction devices

Seiji Yasuda; Mamoru Kurata

Abstract A two-dimensional Poisson equation is solved for a reverse biased p-n junction diode structure without introducing a cumbersome movable boundary treatment of depletion layer edge determination. An investigation is made of the field distribution of a glass-passivated transistor having sidewalls perpendicular to the junction plane. The influences of the glass dielectric constants and glass charge densities will be studied. Positive charges in the glass are shown to induce an undesirable high field near the semiconductor surface and degrade the device breakdown characteristics. The peak field value due to the positive charges increases as the glass dielectric constant decreases. An estimate for permissible operating voltage is obtained for various conditions.


Solid-state Electronics | 2002

ESD protection device design using statistical methods

Naoyuki Shigyo; Hirobumi Kawashima; Seiji Yasuda

Abstract This paper describes a design of the electrostatic discharge (ESD) protection device to minimize its area A p while maintaining the breakdown voltage V ESD . Hypothesis tests using measured data were performed to find the severest applied serge condition and to select control factors for the design-of-experiments (DOE). Also, technology CAD (TCAD) was used to estimate V ESD . An optimum device structure, where salicide block was employed, was found using statistical methods and TCAD.


international symposium on quality electronic design | 2002

Design of ESD protection device using statistical methods

Naoyuki Shigyo; Hirobumi Kawashima; Seiji Yasuda

This paper describes an ESD protection device design to minimize its area A/sub p/ while maintaining the breakdown voltage V/sub ESD/. Hypothesis tests were performed to find the applied surge condition and to select control factors for the design-of-experiments (DOE). Also, TCAD was used to estimate V/sub ESD/. An optimum device structure, where a salicide block was employed, was found using statistical methods and TCAD.


Archive | 1984

Semiconductor device monolithically comprising a V-MOSFET and bipolar transistor isolated from each other

Seiji Yasuda; Toshio Yonezawa; Shunichi Hiraki; Masafumi Miyagawa


Archive | 1988

Evaluation method for semiconductor device

Yoshiro Baba; Yutaka Koshino; Seiji Yasuda


Archive | 1983

Semiconductor device with compact isolation and method of making the same

Yutaka Koshino; Seiji Yasuda; Takashi Ajima; Toshio Yonezawa


Archive | 1980

Semiconductor device comprising an interconnection electrode and method of manufacturing the same

Jiro Oshima; Masaharu Aoyama; Seiji Yasuda; Toshio Yonezawa

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