M. Norishima

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 0.9 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed, standby power and chip area.

A study of nonequilibrium diffusion modeling-applications to rapid thermal annealing and advanced bipolar technologies

A nonequilibrium diffusion model has been developed to study the influence of point defects on dopant redistribution, especially for transient enhanced diffusion. The coupled equations for point defects, substitutional impurities, and impurities/point defect pairs are solved under nonequilibriums condition. Charged species are included and the Poisson equation is solved. The characteristics and domain of validity of this model have been investigated. Indications are suggested to predict the conditions under which a steady-state model can be used. In the case of high-concentration predisposition, enhanced diffusion is observed and concave or exponential profiles are obtained for very short-time diffusion. Applications are presented for oxide diffusion sources. The generality of the model is confirmed by long-time diffusion behavior and by the influence of phosphorus diffusion on the boron buried layer. Anomalous effects observed during RTA steps after ion implantation are also well reproduced by the model. Successful comparisons with experiments are reported for boron and for actual bipolar structures, with coupled arsenic/boron diffusion in a 0.5- mu m BiCMOS process. >

Impurity diffusion behavior of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5- mu m Bi-CMOS process

A low-temperature-processed (800-850 degrees C) bipolar transistor design suitable for the high-performance 0.5- mu m BiCMOS process is discussed. It has been found that insufficient activation of arsenic in the emitter, enhanced boron diffusion in the low-concentration base region. and insufficient arsenic diffusion from the poly Si are serious considerations if low-temperature furnace annealing is used. If high-temperature rapid thermal annealing (RTA) is used instead of low-temperature furnace annealing, these problems are resolved. Through impurity diffusion behavior and related electrical bipolar transistor design in the high-performance 0. 5- mu m Bi-CMOS process are proposed. The As-P emitter and selectively implanted collector structures, annealed using RTA, were found to be suitable for the advanced Bi-CMOS process. >

Minority carrier mobility model for device simulation

Abstract We present a new mobility model which incorporates a minority carrier mobility, for semiconductor device simulation. Mobility model used in device simulators is traditionally a function of the total impurity concentration. However, the proposed model is not a function of the total impurity concentration. This new model is implemented in a triangular-mesh device simulator, TRIMEDES. Simulated BJT current-voltage characteristics using the proposed model reveal excellent agreement with measurement.

Bipolar transistor design for low process-temperature 0.5 mu m Bi-CMOS

A low-temperature (800-850 degrees C) processes bipolar transistor design suitable for high-performance 0.5- mu m BiCMOS process is discussed. It was found that insufficient activation of arsenic in the emitter, fast base boron diffusion in the low-concentration region caused by implantation damages for the direct-ion-implanted emitter case, and insufficient arsenic diffusion from the poly-Si for the poly-Si emitter case should be considered as serious problems when the low-temperature furnace anneal is used. High-temperature RTA (rapid thermal annealing) is shown to solve those problems. Based on the impurity diffusion behaviors and related electric bipolar characteristics, the optimum conditions and structures for bipolar transistor design for the high-performance 0.5- mu m BiCMOS process are discussed.<<ETX>>

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8- mu m BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical). >

A 3.3 V, 0.5 mu m BiCMOS technology for BiNMOS and ECL gates

A 0.5- mu m BiCMOS technology for achieving speed performance with scaling is described. For the lower supply voltage of 3.3 V, the delay time of the conventional BiCMOS gate becomes almost equal to that of the CMOS gate. A BiNMOS circuit was employed and achieved a speed advantage over the CMOS at 3.3 V. To improve bipolar performance and its ECL (emitter coupled logic) gate delay time, a selectively ion-implanted collector technology, was investigated and a quasi-self-aligned bipolar transistor with double polysilicon layers was utilized. The ECL gave achieved a delay time of 57 ps/stage. Both gates retained the speed performance for the scaling trend.<<ETX>>

Comparison between poly emitter bipolar characteristics with and without native oxide layers under various processes

The effect of the interfacial native oxide layer between polycrystalline and single-crystal Si was investigated in the submicron-rule bipolar and BiCMOS processes. It was found that the native oxide increases the current gain, but significantly degrades bipolar transistor performance. Bipolar transistors without the oxide layer, fabricated by different methods, were investigated. Without the layer, low emitter resistance and small current gain variation were achieved for a low-temperature process. The current gain reduction due to the lack of the oxide layer does not degrade the cutoff frequency. Improved performance for structures without native oxide was confirmed with ECL (emitter-coupled logic) ring oscillators.<<ETX>>

High-performance 0.5 mu m CMOS technology for logic LSIs with embedded large capacity SRAMs

The optimum device design of 0.5 mu m CMOS for logic LSIs with embedded large-capacity SRAMs (static RAMs) with a 3.3 V supply voltage is proposed. In order to attain high performance with a 3.3 V supply, the p-MOSFET structure was designed and the gate oxide thickness and junction capacitance were optimized. A poly-Si load SRAM cell with a triple-well structure on p-substrate, WSi-polycide gate electrode, and triple-level metallization with W plug via holes were implemented. By careful design of each parameter and proper integration of the technologies, a high-performance 0.5 mu m CMOS with large-capacity cache memories was realized.<<ETX>>

Impact of ion-implantation damage and transient-enhanced diffusion on advanced bipolar technologies-comparisons between experiments and non-equilibrium diffusion modeling

The influence of ion-implantation damage on the formation of emitter and base in advanced bipolar technologies is studied. A novel nonequilibrium diffusion model has been developed to analyze this issue. By comparing simulation and experiments on a 0.5- mu m BiCMOS technology, transient-enhanced diffusion phenomena for rapid thermal anneal and furnace annealing are discussed. Two-dimensional effects are reported.<<ETX>>