Naoyuki Shigyo

Effects of microscopic fluctuations in dopant distributions on MOSFET threshold voltage

The effects of fluctuations in dopant distribution on the MOSFET threshold voltage and their dependence on the scaling were investigated using device simulation. The simulation indicates that the microscopic fluctuations in dopant distribution not only induce threshold-voltage value. It was found that the threshold-voltage value deviation is mostly affected by fluctuating dopant distribution at the substrate surface, rather than throughout the depletion layer. Discussion incorporating microscopic fluctuations in surface electric potential, due to fluctuating dopant distribution, explained not only deviations but also the mean value lowering of the threshold voltage in the simulation. >

Technology trends of silicon-on-insulator-its advantages and problems to be solved

Recent progress in SOI technology is reviewed and problems which need be solved are discussed. Emphasis is placed on the substrate floating effect, for which the bandgap engineering method is proposed for the first time. It is demonstrated that Si-Ge formation in the source region can improve the drain breakdown voltage significantly.<<ETX>>

A ULSI 2-D capacitance simulator for complex structures based on actual processes

A two-dimensional (2-D) capacitance simulator for ultra-large-scale integrated (ULSI) circuits using an improved boundary-element method (BEM) is described. The capacitance simulator was linked with a topography/process simulator to estimate the distributed capacitances of complex structures based on actual processes. The utilization of a linear discontinuous element as the shape function is proposed in order to deal with multiregional problems by BEM. Other techniques employed in the simulation program, which enable precise calculation within practical CPU time, are also described. The calculated capacitances show good agreement with the experimental results. >

Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si/sub 1-x/Ge/sub x/ source structure

The bandgap engineering method using a SiGe source structure is presented as a means to suppress the floating-body effect in SOI MOSFETs. Experiments using Ge implantation are carried out to form a narrow-bandgapped SiGe layer in the source region. It has been confirmed that Ge-implanted SIMOX exhibited a 0.1 eV bandgap narrowing with a relatively low Ge-dosage of 10/sup 16/ cm/sup -2/. The fabricated N-type SOI-MOSFETs exhibited suppressed parasitic bipolar effects, such as improvement of the drain breakdown voltage or latch voltage, and suppression of abnormal subthreshold slope. Advantages over other conventional methods are also discussed, indicating that the bandgap engineering provides a practical method to suppress the floating-body effect.

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

The dependence of MOSFET gate controllability on the field-isolation scheme is investigated using three-dimensional simulation. It is found that a fully-recessed-oxide (trench) isolated MOSFET has a steep subthreshold characteristic and high transconductance in comparison with a nonrecessed device. These features result from the small depletion capacitance due to the crowding of the gates fringing field at the channel edge. It is also found that the gate and diffused line capacitances in the case of fully-recessed-oxide isolation are small, so that high switching speed operation can be expected. These features are enhanced with a reduction in the channel width, especially for lower-submicrometer-width MOSFETs. A drawback of a fully-recessed-oxide MOSFETs is its low threshold voltage. However, the leakage current is not as large as that inferred from the inverse narrow-channel effect because of its steep subthreshold characteristic. Several countermeasures for this low threshold voltage are discussed. >

A study of nonequilibrium diffusion modeling-applications to rapid thermal annealing and advanced bipolar technologies

A nonequilibrium diffusion model has been developed to study the influence of point defects on dopant redistribution, especially for transient enhanced diffusion. The coupled equations for point defects, substitutional impurities, and impurities/point defect pairs are solved under nonequilibriums condition. Charged species are included and the Poisson equation is solved. The characteristics and domain of validity of this model have been investigated. Indications are suggested to predict the conditions under which a steady-state model can be used. In the case of high-concentration predisposition, enhanced diffusion is observed and concave or exponential profiles are obtained for very short-time diffusion. Applications are presented for oxide diffusion sources. The generality of the model is confirmed by long-time diffusion behavior and by the influence of phosphorus diffusion on the boron buried layer. Anomalous effects observed during RTA steps after ion implantation are also well reproduced by the model. Successful comparisons with experiments are reported for boron and for actual bipolar structures, with coupled arsenic/boron diffusion in a 0.5- mu m BiCMOS process. >

A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases

Abstract The shallow trench isolation (STI) is one of the key technologies for VLSI. The threshold voltage Vth for surface-channel STI MOSFETs becomes lower with decreasing channel width W, which is called the inverse narrow-channel effect (INCE). Also, there is a hump in the subthreshold characteristic. On the contrary, buried-channel STI MOSFETs reveal a conventional narrow-channel effect. Also, there is no hump in the subthreshold characteristic. This paper reviews above phenomena with a consistent explanation for the surface- and buried-channel STI MOSFETs. Countermeasures for INCE are also discussed.

Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations

This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed.

Verification of overlap and fringing capacitance models for MOSFETs

Abstract Parasitic capacitance and resistance limit the VLSI device performance. Hence, a circuit model is needed to treat these effects correctly. This article focuses on the circuit models for the overlap capacitance ( C gd,overlap ) and the fringing capacitance ( C gd,fringe ) of MOSFETs. Comparisons between the models and the device simulations are carried out for verification of the models. Also, a limitation of C gd,fringe model for a future device miniaturization is found based on SIA Road Map. We propose a modified C gd,fringe model. The effectiveness of the modified model is demonstrated using two circuits.

Discretization error in MOSFET device simulation

The discretization error in MOSFET device simulation caused by a coarse grid is discussed. Delaunay and Voronoi discretization grids are used to demonstrate the discretization error. It is possible to clarify the discretization error by using these geometrically complementary grids. An error caused by a coarse grid in the subthreshold region originates from an inaccurate rectangular integral of the carrier density. For the Delaunay grid, the calculated inversion carrier density for a coarse grid is overestimated. In contrast, for the Voronoi grid, the inversion carrier density is underestimated. The equations for estimating the error in the subthreshold region are proposed. In the strong inversion region, the error for the Delaunay grid is smaller than the error in the subthreshold region. On the other hand, for the Voronoi grid, the error is large, even in the strong inversion region. The error for the Voronoi grid in the strong inversion region is caused by a quasi-capacitance originating from discretization. >