Seon-Yong Cha

RTS-like fluctuation in Gate Induced Drain Leakage current of Saddle-Fin type DRAM cell transistor

RTS (random telegraph signal)-like fluctuation in Gate Induced Drain Leakage (GIDL) current of Saddle-Fin (S-Fin) type DRAM cell transistor was investigated for the first time. Furthermore, two types of fluctuation which have apparently different τhigh (average time duration of high leakage state) to τlow (average time duration of low leakage state) ratio were investigated, and it was found that the energy difference between bistable levels is similar to that of the junction leakage.

Characterization of the Variable Retention Time in Dynamic Random Access Memory

To study the relationship between the original leakage current fluctuation and the detected variable retention time (VRT) from the retention test of dynamic random access memory (DRAM), we simulated the real procedure of the VRT measurement of DRAM. By investigating the results of the simulation, we proposed a new effective VRT measurement method based on the comparison between measurement and simulation. In addition, we investigated the characteristics of the VRT phenomenon in DRAM using the VRT characterization method developed in this study.

Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

To study trap models related to the variable retention time (VRT) phenomenon in dynamic random access memory (DRAM), we derived equations to calculate the data retention time tret of DRAM and the activation energy for two trap models, i.e., the metastable and oxide trap models. Measuring the tret of VRT cells for various bias and temperature conditions, the dependence of activation energy differences in tret on bias at high and low retention states was extracted. Furthermore, the dependence of the electric field on bias at high and low retention states was also extracted. Using those parameters, we successfully distinguished the two types of trap models.

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

We generated traps inside gate oxide in gate–drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler–Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal–oxide–semiconductor field-effect transistors (MOSFETs).

Effectiveness of a Guard Ring Utilizing an Inversion Layer Surrounding a Through Silicon Via

We characterize quantitatively a guard ring of a through-silicon via (TSV) which is used to reduce the coupling noise from the TSV by utilizing an inversion layer as a shield layer. The proposed guard ring consists of a shallow n+ region, a deep n- well, and an inversion layer formed along the interface between the oxide surrounding the TSV and the p-substrate. The coupling noise induced by the TSV is reduced by approximately one order of magnitude in the near-threshold region of the victim nMOS, which is located at 10 μm away from the TSV. The proposed guard ring is characterized as the distance between the TSV and the victim nMOS in a comparison with cases without a guard ring and with a conventional p+ guard ring. The proposed method reduces the drain current fluctuation by ~61% compared with the case with the conventional p+ guard ring.

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (Dit). It is worthwhile to note that the Dit as well as the GIDL current is a still meaning parameter to analyze the data retention time.

Study on the Vt variation and bias temperature instability characteristics of TiN/W and TiN metal buried-gate transistor in DRAM application

The Vt variation and positive bias temperature instability (PBTI) of TiN/W and TiN metal buried-gate (BG) cell transistors in DRAM are characterized. The use of TiN gate shows a larger Vt variation and different PBTI behavior as compared with TiN/W gate and these are attributed to the formation of chlorine (Cl)-related trap sites during the etch-back process of metal gate. This indicates that Cl in the chemical vapor deposition (CVD) TiN gate is responsible for the phenomena.

A Study of Flash Anneal in combination with the conventional RTA for DRAM application

We have investigated the effects of FLA technique on the DRAM peripheral transistor improvements by integrating into the SDRTA (Source/Drain RTA) and ADD RTA (Add RTA after contact formation). FLA with conventional RTA was not effective because of SCE (Short Channel Effect) control. FLA only was effective to improve SCE and Iop, and especially more effective on technology shrink. By flash anneal (FLA), we tried to achieve better activation, lower series resistance and less dopant loss. For higher activation, the pre‐heat temperature of FLA was varied by 50 °C higher or lower than the desired base temperature. For lower resistance, the sidewall spacer thickness was reduced by 50 A, 100 A and 150 A. For reducing dopant loss during the contact etch process, the deeper S/D Rp was used by increasing the S/D implant energy with an increased Rp by 150 A, 200 A and 250 A. Results with FLA base show 13.4% improvement, and at the higher pre‐heat temperature, it can be improved to 16.9%. In conclusion, FLA can be on...

Study on the Sub-Threshold Margin Characteristics of the Extremely Scaled 3-D DRAM Cell Transistors

This paper proposes an equivalent circuit model of 3-D DRAM cell transistors with recess gate and saddle fin structure for the first time. The model effectively characterize the sub-threshold and off margin behavior of the scaled DRAM cell transistor by considering the parasitic sub-channel and vertical transistor components into account. TCAD simulation and experimental data have confirmed the accuracy of the model. With the analysis made, we suggest a set of improvement method for the off margin characteristics engineering. These methods are believed to lead the continuous DRAM scaling, down to sub-10nm technology node.

Mobility Enhancement of Peripheral PMOSFET Using e-SiGe Source and Drain in Sub-50nm DRAM

The mobility enhanced pMOS transistors have been successfully implemented into sub-50nm DRAM for the first time. The uni-axial strained channels were embodied by filling the recessed source/drain with epitaxial SiGe film. Mobility boosting and reduced external resistance enabled pMOS transistors to increase saturation current by 20%, and retarded boron diffusion reduced DIBL by 17mV/V compared to control process without degradation of DRAM cell data retention time characteristics. The local variation of threshold voltage is suppressed to the same level of control process. The hot electron induced punch-through (HEIP) degradation can be controlled to negligible degree.