Jae-Goan Jeong

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dry-etching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology

A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the Fowler-Nordheim (F-N) and hot carrier stresses for the recently developed dynamic random-access memory cell transistors with deeply recessed channels. We have identified the important differences in the leakage mechanism between saddle fin (S-Fin) and recess channel array transistor (RCAT). These devices have their own respective structural benefits with regard to leakage current. Therefore, we suggest guidelines with respect to the optimal device structures such that they have the advantages of both S-Fin and RCAT structures. With these guidelines, we propose a new recess-FinFET structure that can be realized by feasible manufacturing process steps. The structure has the side-gate form only in the bottom channel region. This enhances the characteristics of the threshold voltage (VTH), ON/OFF currents, and the retention time distributions compared with the S-Fin structure introduced recently.

Characterization of the Variable Retention Time in Dynamic Random Access Memory

To study the relationship between the original leakage current fluctuation and the detected variable retention time (VRT) from the retention test of dynamic random access memory (DRAM), we simulated the real procedure of the VRT measurement of DRAM. By investigating the results of the simulation, we proposed a new effective VRT measurement method based on the comparison between measurement and simulation. In addition, we investigated the characteristics of the VRT phenomenon in DRAM using the VRT characterization method developed in this study.

Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

To study trap models related to the variable retention time (VRT) phenomenon in dynamic random access memory (DRAM), we derived equations to calculate the data retention time tret of DRAM and the activation energy for two trap models, i.e., the metastable and oxide trap models. Measuring the tret of VRT cells for various bias and temperature conditions, the dependence of activation energy differences in tret on bias at high and low retention states was extracted. Furthermore, the dependence of the electric field on bias at high and low retention states was also extracted. Using those parameters, we successfully distinguished the two types of trap models.

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

We generated traps inside gate oxide in gate–drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler–Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal–oxide–semiconductor field-effect transistors (MOSFETs).

Requirements of bipolar switching ReRAM for 1T1R type high density memory array

ReRAM has been researched as a promising candidate for diverse NVM application [1]. Still switching mechanism and classification are not clear, there are simply two kinds of switching polarity: unipolar and bipolar. Considering distribution, operation margin and so on, bipolar switching looks much attractive than unipolar. Along with a selective device, polarity of switching could make the architecture of cell array different. The Crossbar array structure has been considered an attractive solution for unipolar switching with diode. To make the crossbar array with bipolar switching devices, research on a new selective device such as MIEC [2] is much necessary to meet the requirements of current drivability and on/off properties. In addition, self-rectifying device [3–4] could be an alternative for a high density crossbar array. Recently, several research groups have shown very fast and high reliable device. It could be a good signal that ReRAM could have speed and endurance for DRAM or embedded applications. In case of those applications, 1T1R structure could be an effective and it could be used to check the feasibility by changing ReRAM cell with capacitor or MTJ. From now on, transistor has been mainly considered as a controller for the compliance current in set process. But the bipolar 1T1R structure for a high density array, there are several things to be considered, because a transistor would be acting as a changeable resistance at a set and reset process and its resistance goes up as the technology shrinks. So in this paper, we tried to figure out the requirements of bipolar ReRAM switching for the high density 1T1R memory array by changing reset current and symmetry of ReRAM devices.

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (Dit). It is worthwhile to note that the Dit as well as the GIDL current is a still meaning parameter to analyze the data retention time.

Study on the Vt variation and bias temperature instability characteristics of TiN/W and TiN metal buried-gate transistor in DRAM application

The Vt variation and positive bias temperature instability (PBTI) of TiN/W and TiN metal buried-gate (BG) cell transistors in DRAM are characterized. The use of TiN gate shows a larger Vt variation and different PBTI behavior as compared with TiN/W gate and these are attributed to the formation of chlorine (Cl)-related trap sites during the etch-back process of metal gate. This indicates that Cl in the chemical vapor deposition (CVD) TiN gate is responsible for the phenomena.

Reliability Studies on Non Planar DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the F-N and hot carrier stresses for the recently developed DRAM cell transistors having deeply recessed channels. We have found the important difference of the leakage mechanism between S-Fin and RCAT, which have each structural benefit in the characteristics of leakage current, so we can suggest the guide lines for device structures simultaneously having each merit in both structures.

Mobility Enhancement of Peripheral PMOSFET Using e-SiGe Source and Drain in Sub-50nm DRAM

The mobility enhanced pMOS transistors have been successfully implemented into sub-50nm DRAM for the first time. The uni-axial strained channels were embodied by filling the recessed source/drain with epitaxial SiGe film. Mobility boosting and reduced external resistance enabled pMOS transistors to increase saturation current by 20%, and retarded boron diffusion reduced DIBL by 17mV/V compared to control process without degradation of DRAM cell data retention time characteristics. The local variation of threshold voltage is suppressed to the same level of control process. The hot electron induced punch-through (HEIP) degradation can be controlled to negligible degree.