Yong-Taik Kim

Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications

4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >;8, Iop <;10uA, Vop<;60;3V), TiOx/Ta2O5, are modified for its working in a chip by adopting appropriate materials for a resistor stack and spacer. Write condition in a chip makes a critical impact on read margin and read/write operation in a chip has been verified.

Study on the Vt variation and bias temperature instability characteristics of TiN/W and TiN metal buried-gate transistor in DRAM application

The Vt variation and positive bias temperature instability (PBTI) of TiN/W and TiN metal buried-gate (BG) cell transistors in DRAM are characterized. The use of TiN gate shows a larger Vt variation and different PBTI behavior as compared with TiN/W gate and these are attributed to the formation of chlorine (Cl)-related trap sites during the etch-back process of metal gate. This indicates that Cl in the chemical vapor deposition (CVD) TiN gate is responsible for the phenomena.

Study on the Sub-Threshold Margin Characteristics of the Extremely Scaled 3-D DRAM Cell Transistors

This paper proposes an equivalent circuit model of 3-D DRAM cell transistors with recess gate and saddle fin structure for the first time. The model effectively characterize the sub-threshold and off margin behavior of the scaled DRAM cell transistor by considering the parasitic sub-channel and vertical transistor components into account. TCAD simulation and experimental data have confirmed the accuracy of the model. With the analysis made, we suggest a set of improvement method for the off margin characteristics engineering. These methods are believed to lead the continuous DRAM scaling, down to sub-10nm technology node.

A novel method to characterize the effect from the diffusion of Cu in through silicon via (TSV)

To characterize electrically the effect of the Cu diffusion in TSVs, a new test pattern is proposed and its effectiveness is verified experimentally. The test pattern has a shallow n+ region formed in an n-well region butted to the TSV dielectric surrounding the TSV. Through the n+/n well region, we can measure the diode and gated diode currents, the charge pumping current, and C-V to accurately analyze the effect. Our approach is demonstrated to be very useful by investigating the Cu diffusion effect in samples with two different barrier metal thicknesses.

STI stress-induced degradation of data retention time in DRAM and a new characterizing method for mechanical stress

The effect of mechanical stress induced by shallow trench isolation (STI) slope on the data retention characteristics of DRAM is investigated and a new electrical parameter for monitoring the mechanical stress is proposed. To maintain high and uniform retention time for the reliable operation of DRAM, the STI slope should not be vertical and should be kept below 86-degree. The new electrical parameter measures the current gain of the parasitic BJT in DRAM cell and shows a strong correlation with the retention time induced by the mechanical stress.