Seong-Sue Kim

Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 /spl mu/m/sup 2/ Local SONOS NVM cell, which has 20 /spl mu/s program and 2 ms erase speed under 5.5 V bias condition, and good reliability without the special algorithms and cell array modifications.

Properties of EUVL masks as a function of capping layer and absorber stack structures

We have fabricated extreme ultraviolet lithography (EUVL) blank masks consisting of a TaN absorber, Ru capping layer, and Mo/Si multilayers using ion-beam sputter deposition and investigated their dependence on capping layer and absorber stack structure. At EUV wavelengths, the reflectivities of the multilayers, including their dependency on the thickness of the capping and absorber layers, are in good agreement with simulation results obtained using Maxwell equations and the refractive indexes of each layer. Ru, one of the most promising capping materials on Mo/Si multilayers due to its resistance to oxidation and selectivity to etching, also shows better EUV reflectivity than Si as a capping layer if we choose a thickness that produces a constructive interference. To meet the reflectivity requirements (⩽ 0.5 %) in the SEMI EUVL mask standard specifications, a TaN absorber at least 70 nm thick should be applied. However, aerial image results simulated by using EM-Suite show that 40 nm is sufficient for the TaN absorber to display the maximum image contrast. In addition, horizontal-vertical (HV) biasing effects due to mask shadowing become negligible if the TaN is reduced to about 40 nm. As a result, we suggest using a thin TaN absorber 40 nm thick since it is able to minimize mask shadowing effects without a loss of image contrast.

Absorber stack optimization in EUVL masks: lithographic performances in alpha demo tool and other issues

Thinner absorber structure in EUVL mask is supposed to be applied in 2x HP node since it shows several advantages including H-V bias reduction. Here, lithographic performances of EUVL masks as a function of absorber stack height are investigated using ADT exposure experiments. Wafer SEM images show that minimum resolution is almost identical at ~27.5 nm with absorber thickness ranging from 45 to 70 nm. Simulations also exhibit that NILS and contrast become maximized and saturated in those ranges. However, thinner absorber structure using 50-nm-thick absorber shows much lower H-V bias than conventional structure using 70-nm-thick absorber. MEEF, EL, DOF, and LWR are also slightly improved with thinner absorber. One of the noticeable issues in thin absorber is low OD which results in pattern damages and CD reduction at shot edges due to light leakage from the neighboring exposures. To overcome these issues, appropriate light shielding process during mask fabrication as well as minimizing OoB radiation in EUVL scanner are required. Another item to prepare for 2x HP node is to increase defect detection sensitivity with 19x nm inspection tools. Thus, absorber stacks with new ARC layer optimized for 19x nm inspection should be developed and applied in EUVL mask blanks.

Effects of mask absorber structures on the extreme ultraviolet lithography

In this paper, the authors present the results of an investigation of the dependence of mask absorber thickness on the extreme ultraviolet lithography (EUVL) and suggest a new mask structure to minimize shadowing effects. For this purpose, several patterned masks with various TaN absorber thicknesses are fabricated using in-house Ru-capped EUVL mask blanks. According to the simulation using practical refractive indices, which are obtained at EUV wavelengths, the absorber thickness can be reduced to that of out-of-phase (ΔΦ=180°) ranges without loss of image contrast and normalized image log slope. Thickness to meet out-of-phase in real mask can be obtained by comparing field spectrum intensity ratio using the EUV coherent scattering microscopy (CSM). 52.4nm in thickness is close to ΔΦ=180° for TaN absorber since it shows the highest 1st/0th order intensity ratio as well as the best resolution in the microfield exposure tool (MET) test. When we apply 40-nm-thick TaN instead of 80-nm-thick TaN, the amounts of H-V bias reduction in wafer scale correspond to 80% (2.46–0.48nm) by CSM and 70% (2.23–0.65nm) by MET test results. Considering the fact that H-V bias in the MET is similar with that of simulation using the resist model, the degree of H-V bias in the alpha demo tool (ADT) is supposed to be much higher than that of MET due to its higher incident angle (θ=6°). Our final goal is to develop a thin absorber EUVL mask which has a low H-V bias, high EUV printability and DUV contrast, and sufficient optical density at the border. To achieve this, blind layer treatment and integration with anti-reflective coating layer are in progress.In this paper, the authors present the results of an investigation of the dependence of mask absorber thickness on the extreme ultraviolet lithography (EUVL) and suggest a new mask structure to minimize shadowing effects. For this purpose, several patterned masks with various TaN absorber thicknesses are fabricated using in-house Ru-capped EUVL mask blanks. According to the simulation using practical refractive indices, which are obtained at EUV wavelengths, the absorber thickness can be reduced to that of out-of-phase (ΔΦ=180°) ranges without loss of image contrast and normalized image log slope. Thickness to meet out-of-phase in real mask can be obtained by comparing field spectrum intensity ratio using the EUV coherent scattering microscopy (CSM). 52.4nm in thickness is close to ΔΦ=180° for TaN absorber since it shows the highest 1st/0th order intensity ratio as well as the best resolution in the microfield exposure tool (MET) test. When we apply 40-nm-thick TaN instead of 80-nm-thick TaN, the amounts ...

Analysis of process margin in EUV mask repair with nano-machining

Reduced design rules demand higher sensitivity of inspection, and thus small defects which did not affect printability before require repair now. The trend is expected to be similar in extreme ultraviolet lithography (EUVL) which is a promising candidate for sub 32 nm node devices due to high printing resolution. The appropriate repair tool for the small defects is a nanomachining system. An area which remains to be studied is the nano-machining system performance regarding repair of the defects without causing multilayer damage. Currently, nanomachining Z-depth controllability is 3 nm while the Ru-capping layer is 2.5 nm thick in a Buffer-less Ru-capped EUV mask. For this report, new repair processes are studied in conjunction with the machining behavior of the different EUVL mask layers. Repair applications to achieve the Edge Placement(EP) and Z-depth controllability for an optimal printability process window are discussed. Repair feasibility was determined using a EUV micro exposure tool (MET) and Actinic Imaging Tool (AIT) to evaluate repairs the 30 nm and 40 nm nodes. Finally, we will report the process margin of the repair through Slitho-EUVTM simulation by controlling side wall angle, Z-depth, and EP (Edge Placement) on the base of 3-dimensional experimental result.

Progress in EUV lithography toward manufacturing

In this article the recent progress in the elements of EUV lithography is presented. Source power around 205W was demonstrated and further scaling up is going on, which is expected to be implemented in the field within 2017. Source availability keeps improving especially due to the introduction of new droplet generator but collector lifetime needs to be verified at each power level. Mask blank defect satisfied the HVM goal. Resist meets the requirements of development purposes and dose needs to be reduced further to satisfy the productivity demand. Pellicle, where both the high transmittance and long lifetime are demanded, needs improvements especially in pellicle membrane. Potential issues in high-NA EUV are discussed including resist, small DOF, stitching, mask infrastructure, whose solutions need to be prepared timely in addition to high-NA exposure tool to enable this technology.

Prospects of DUV OoB suppression techniques in EUV lithography

Though scaling of source power is still the biggest challenge in EUV lithography (EUVL) technology era, CD and overlay controls for transistor‟s requirement are also precondition of adopting EUVL in mass production. Two kinds of contributors are identified as risks for CDU and Overlay: Infrared (IR) and deep ultraviolet (DUV) out of band (OOB) radiations from laser produced plasma (LPP) EUV source. IR from plasma generating CO2 laser that causes optics heating and wafer overlay error is well suppressed by introducing grating on collector to diffract IR off the optical axis and is the effect has been confirmed by operation of pre-production tool (NXE3100). EUV and DUV OOB which are reflected from mask black boarder (BB) are root causes of EUV-specific CD error at the boundaries of exposed shots which would result in the problem of CDU out of spec unless sufficiently suppressed. Therefore, control of DUV OOB reflection from the mask BB is one of the key technologies that must be developed prior to EUV mass production. In this paper, quantitative assessment on the advantage and the disadvantage of potential OOB solutions will be discussed. EUV and DUV OOB impacts on wafer CDs are measured from NXE3100 & NXE3300 experiments. Significant increase of DUV OOB impact on CD from NXE3300 compared with NXE3100 is observed. There are three ways of technology being developed to suppress DUV OOB: spectral purity filter (SPF) as a scanner solution, multi-layer etching as a solution on mask, and resist top-coating as a process solution. PROs and CONs of on-scanner, on-mask, and on-resist solution for the mass production of EUV lithography will be discussed.

Ruthenium (Ru) peeling and predicting robustness of the capping layer using finite element method (FEM) modeling

Ruthenium (Ru) film used as capping layer in extreme ultraviolet (EUV) mask peeled off after annealing and in-situ UV (IUV) cleaning. We investigated Ru peeling and found out that the mechanical stress caused by the formation of Si oxide due to the penetration of oxygen atoms from ambient or cleaning media to top-Si of ML is the root cause for the problem. To support our experimental results, we developed a numerical model of finite element method (FEM) using commercial software (ABAQUS™) to calculate the stress and displacement forced on the capping layer. By using this model, we could observe that the displacement agrees well with the actual results measured from the transmission electron microscopy (TEM) image. Using the ion beam deposition (IBD) tool at SEMATECH, we developed four new types of alternative capping materials (RuA, RuB, B4C, B4C-buffered Ru). The durability of each new alternative capping layer observed by experiment was better than that of conventional Ru. The stress and displacement calculated from each new alternative capping layer, using modeling, also agreed well with the experimental results. A new EUV mask structure is proposed, inserting a layer of B4C (B4C-buffered Ru) at the interface between the capping layer (Ru) and the top-Si layer. The modeling results showed that the maximum displacement and bending stress observed from the B4C-buffered Ru are significantly lower than that of single capping layer cases. The durability investigated from the experiment also showed that the B4C-buffered structure is at least 3X stronger than that of conventional Ru.

Angular Dependence of the Etch Rates of TaN in CF4 / Ar and CHF3 / Ar Plasmas

The etching characteristics of tantalum nitride (TaN), a mask absorber in extreme UV lithography, was investigated by observing the angular dependence of its normalized etch yield in CF 4 /Ar and CHF 3 /Ar inductively coupled plasmas (ICPs). The direction of plasma ions incident on the substrate surface was controlled in a specially designed etcher that contained a Faraday cage and substrate holders of different slope angles. Experiments performed at different ICP powers, combined with analyses of the sample surface by X-ray photoelectron spectroscopy and plasma gases by optical emission spectroscopy, showed that as the ICP power increased, the mechanism involved in the etching of the TaN substrate changed from physical sputtering to chemical sputtering in a CF 4 plasma while the mechanism changed from chemical sputtering to physical sputtering in a CHF 3 plasma. A tantalum native oxide film formed on the substrate surface decreased the etch rates by suppressing the transfer of ionic momentum to TaN. However, hydrogen atoms present in a CHF 3 plasma reduced the thickness of the oxide layer and consequently enhanced the etch rates of the substrate.

Measurement technique of nontelecentricity of pupil-fill and its application to 60 nm NAND flash memory patterns

Various pupil-fill measurement techniques are evaluated to monitor non-telecentricity of an illuminator as followings: transmission image sensor (TIS) of ASML, source metrology instrument (SMI) of Litel, Fresnel zone plate (FZP) of Philips, and non-telecentricity measurement technique using traditional overlay marks, which is based on an idea that pattern shift is proportional to the amount of defocus. Based on aerial image simulation with measured non-telecentricity, its effect on sub-70 nm device patterning is discussed. Experimental data shows that some of pupil-fills appear more than 70 milli-radian of source displacement error and it may cause serious pattern shift and/or asymmetry. Detailed descriptions of measurement techniques and experimental results are presented.