Ser Choong Chong

Si -based microphone testing methodology and noise reduction

In this paper two different packaging and testing approaches were studied for Si based microphone. Microphone performance was tested with Ceramic, Plastic and metal packages. Sensitivity testing of microphone is done when it is connected to an ASIC die. Testing was done with microphone and ASIC packaged separately and also in a single package. Substantial noise was generated when microphone and ASIC are tested separately in a PCB. Noise was detected after 150 Hz with the noise intensity reducing as it goes to higher frequencies. This was observed regardless of the packaging schemes. Different shielding methods were tried and found that copper foil shielding results in substantial noise reduction during frequency response testing and a flat response curve was observed with metal can package. Form this new testing methodology, it is demonstrated that same ASIC can be used repeatedly during microphone testing and hence some cost reduction can be expected.

Vacuum packaging development and testing for an uncooled IR bolometer device

A vacuum package has been developed for 128/spl times/128 array IR bolometer device with Ge window having anti reflection (AR) coating. For a good vacuum package hermeticity and low out gassing are the two critical elements. A good hermetic sealing has been achieved with Ge window attachment using solder bonding. Different metallization structures have been tried and metallization of oxide/Ti/Ni/Au with additional annealing process was found to have good adhesion and solder wetting. Getters have been activated before final vacuum sealing of the package to absorb the outgassing gases from the packaging materials. Residual Gas analysis (RGA) showed that Thermo electric cooler used inside the package outgassed more compared to other materials. Vacuum inside the package was measured by using a single element IR bolometer device and found to have vacuum of 50milli torr. The developed vacuum package has been tested functionally and found to be no degradation in image before and after packaging.

Double side redistribution layer process on embedded wafer level package for package on package (PoP) applications

In this paper, an embedded wafer level package with Cu through mold via (TMV) interconnects was developed for package on package (PoP) application. Cu pillar interconnects for different heights were fabricated on daisy chain test chips and sacrificial chips. The daisy chain test chips were then stacked onto the sacrificial chips using die attach film, and the chip stacks were picked and placed onto a molding tape for mold encapsulation to form a re-configured wafer. The reconfigured wafer was mechanically backgrinded on both sides to remove sacrificial chips and to expose the Cu TMV. The thinned re-configured wafer was temporarily bonded to a stiff Si carrier using a temporary adhesive, in order to reduce the wafer warpage to enable wafer level processing of the Cu redistribution layers (RDL). After front side RDL processing, the re-configured wafer is de-bonded and re-bonded for backside RDL processing. The warpage value of the reconfigured wafer was measured during different process steps and through-scan was performed using a scanning acoustic microscope to inspect the quality of temporary bonding of re-configured wafers to a Si carrier. Electrical test shows good connectivity between front and back side RDL with Cu TMV, thus enabling embedding wafer level package for PoP application.

Process challenges and development of eWLP

Embedded Wafer Level Package (eWLP) is designed and developed. The eWLP consists of one silicon die encapsulated with a mold compound and its size is 12mm × 12mm × 0.2mm. The assembly process of eWLP consists of reconfiguration of the dies on an adhesive tape, followed by molding, thinning and rerouting distribution layer (RDL) process. Finite Element Modeling (FEM) is used to understand the stress distribution in the eWLP and provide design input to the configuration of eWLP. The encapsulated eWLP passed 1000 air-to-air thermal cycles (−40 to 125°C), unbiased Highly Accelerated Stress Test (HAST) and moisture sensitivity level 3 (MSL3) test. In this paper, FEM of eWLP, selection of granular epoxy mold compound (EMC), die shift analysis, and warpage study will be discussed in detail.

3D stacking by hybrid bonding with low temperature solder

Three dimensional (3D) IC integration technologies have become essential as the market demands for product with low power consumption, multi functions, smaller size and faster response have been increasing. 3D stacking with conventional high melting temperature solders such as SnAg and Sn may induce high thermal stress to the package. In this paper, chip to chip 3D stacking using no flow underfill material and low temperature solder is demonstrated. The stacking of 100µm thin chips with 7mm×7mm size onto 350µm thin substrate with 10mm×10mm size at 100µm bump pitch was developed. Indium base solder was used to allow low temperature (<200°C) integration. Two types of underfill material were evaluated in terms of their shear strength and interfacial quality through C-SAM results before and after reliability test. Optimization of dispensing process parameters has been performed. The effect of bonding process parameters such as temperature, force and time on bonding strength has been analyzed by design of experiment (DOE) study and optimal bonding condition has been achieved. Quality of solder joints was assessed in terms of shear strength, microstructure and compositional observations of by means of X-Ray inspection, destructive shear test, cross-section analysis and scanning electron microscope (SEM).

Development of Via in Mold (ViM) for embedded wafer level package (EWMLP)

In this paper, a Via in Mold (ViM) interconnects were developed for embedded wafer level package (EMWLP) to enable 3D application. ViM interconnects are essentially plated blind vias drilled into the mold compound substrate. The two key processes required for ViM development are laser drilling of blind vias and Cu seed layer deposition. Mold compound is a composite material made up of epoxy resin and filler particles. The non-uniform distribution of filler particles in the matrix will make consistent laser drilling results difficult to achieve. Laser drilling process parameters were optimized such that the drilling depth is stopped at the Cu metallization pads without damaging the metallization. The sidewall roughness of laser drilled vias makes it difficult for physical vapor deposition process to achieve a conformal seed layer. In order to overcome issues with rough vias sidewall, an electroless Cu plating process was adopted. Electroless Cu plating process was optimized to deposit a conformal Cu seed layer along the sidewall. Electrolytic Cu plating was used to build up the electroless Cu seed layer to the desired thickness for electrical connection. A test vehicle which consists of 50 via-chains was fabricated using the optimized process parameters. The via-chains electrical resistance was measured to extract the resistance of a single ViM. From the electrical resistance measurement, the resistance for a single ViM is ∼0.02 Ω.

Disposable Polydimethylsioxane Package for 'Bio~Microfluidic System'

A disposable polydimethylsioxane package is developed for ‘Bio-Microfluidic System’. Disposable Bio-Microfluidic system avoids the contamination of the system after each use and this requires the use of low cost materials. Polydimethylsioxane (PDMS) is an attractive low cost material for making substrates of the micro-fluidic package. The disposable PDMS Package consists of PDMS substrates, which are fabricated by soft-lithography. The PDMS substrates are bonded together to form the disposable package with the use of a thin-film, coated both side with adhesive material. The adhesive material is selected by chemical soaking test, peel test and bio-analysis. The tests reveal that the adhesive material can handle all chemical reagents without causing blockage or discoloration to the package. The disposable PDMS package uses a plug-in concept as the macro-micro fluidic interconnects that allows easy detachment of package from the external fluidic system. The developed disposable PDMS package has demonstrated a fluidic leak-proof package that handles up to 100kPa pressure with flow-rate of 200µl/min. The package has also demonstrated that it can filter out Viral Ribonucleic Acids (RNA) from spiked blood sample. This micro fluidic package forms an integral part of the bio micro fluidic system.

Solder joint encapsulation and reliability using dippable underfill

The demand for flip chip devices is rising to meet increasingly strict requirements for smaller package size, multiple-die stacking and higher interconnection densities. There are, however, two major issues facing the flip chip process, which are reliability impact by the stresses induced in the solder joints during reflow and high cost for underfill process and materials. Current alternatives to capillary underfill for Pb-free products such as wafer-level underfill and no-flow underfill introduce additional and low-yield process steps. The new dipping adhesive incorporates underfill in attach-and-reflow step and protects each Pb-free solder joint individually, thus enhancing joint reliability. The dippable underfill (DUF) has potential applications in fine-pitch and fine-gap chip-to-chip (C2C) and chip to wafer (C2W) stacked Pb-free packages, as conventional capillary underfill may not be able to achieve void-free underfilling due to the ultra-fine gap, for instance, less than 10µm. Cost reduction is also achieved because expensive capillary underfill material and equipment is not required anymore. Less material is used in solder joint encapsulation compared to fully-filled capillary underfill (CUF). Lastly, due to the reduction in the number of process steps, the process yield is improved while the process time is also reduced. This is especially important for high-volume production and can result in substantial cost savings. In addition, finite element analysis (FEA) was conducted to investigate the effect of dippable underfill on solder joint reliability. Simulation results showed that dippable underfill results in higher solder joint thermal fatigue life.

Low standoff Chip to Wafer bonding

Industry is moving towards having module with multiple functions and capabilities in order to satisfy consumer demands. Miniaturized the package will allowed more components to pack inside the electronic gadget. A low z-foot print of the package is one of the approaches to miniaturize the package. The adoption of micro-bump solders in the chip allowed low standoff Chip to Wafer (C2W) solder interconnects. The chip used in this study is of size 12mm × 12mm × 0.07mm and consists of array of micro-solder bumps at 80µm pitch and 50µm UBM diameter. The wafer is of 200mm diameter and 0.7mm thick.

Design and fabrication of embedded passives on thin flexible substrates and reliability evaluation of passives performance

Recent trends favour the widespread adoption of RFID technology for supply chain and retail applications [1]. To be economically viable, the tags have to be manufactured with a low unit cost. Thus, a fabrication technology which involves inexpensive processes is highly desirable. This work discusses the design and fabrication of embedded passives on flex. In particular, some guidelines are provided for the design of inductors. Lastly, the passives were subjected to some reliability evaluation and their performance ascertained.