Shiuh-Wuu Lee

A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing process variations are included, with demonstrations on two representatives (RO and SRAM) under realistic digital circuit operations. The proposed approach and the results are helpful for robust and resilient device/circuit co-design in future nano-CMOS technology.

New insights into AC RTN in scaled high-к / metal-gate MOSFETs under digital circuit operations

Since devices actually operate under AC signals in digital circuits, it is more informative to study random telegraph noise (RTN) at dynamic AC biases than at constant DC voltages. We found that the AC RTN statistics largely deviates from traditional DC RTN, in terms of different distribution functions and the strong dependence on AC signal frequency, which directly impacts on the accurate prediction of circuit stability and variability. The AC RTN characteristics in high-κ/metal-gate FETs are different from that in SiON FETs, and both of which cannot be described by classical RTN theory. A physical model based on quantum mechanics is proposed, which successfully explains the new observations of AC RTN. It is also demonstrated that, if using DC RTN statistics instead of AC RTN, a large error of 30% overestimation on the read failure probability in ultra-scaled SRAM cells will occur. These new understandings are critical for the robust circuit design against RTN in practical digital circuits.

New observations on AC NBTI induced dynamic variability in scaled high-κ/Metal-gate MOSFETs: Characterization, origin of frequency dependence, and impacts on circuits

In this paper, the frequency dependence of the dynamic variation induced by AC NBTI aging in scaled high-κ/metal-gate devices are experimentally studied for the first time. Challenges in comprehensively characterizing AC NBTI induced variation are addressed by the modified method. The additional variation source in AC NBTI, originating from the variations among each AC clock cycle, is found to be non-negligible and thus should be included in predicting circuit stability. With increasing AC frequency, the mean value (μ) of the Vth shift (ΔVth) is reduced as expected; however, the variation (σ) of ΔVth is almost unchanged, which surprisingly disagrees with the conventional model predicting the reduced variation. The origin of this new observation is found due to the competitive impacts of the activated trap number and the trap occupancy probability during device aging. Taken clock-CCV and frequency dependence into account, the impacts of AC NBTI on the SRAM cell stability can be evaluated in terms of both degradation and variation. The results are helpful for the future variability-aware circuit design.

New insights into the design for end-of-life variability of NBTI in scaled high-κ/metal-gate Technology for the nano-reliability era

In this paper, a new methodology for the assessment of end-of-life variability of NBTI is proposed for the first time. By introducing the concept of characteristic failure probability, the uncertainty in the predicted 10-year VDD is addressed. Based on this, variability resulted from NBTI degradation at end of life under specific VDD is extensively studied with a novel characterization technique. With the further circuit level analysis based on this new methodology, the timing margin can be relaxed. The new methodology has also been extended to FinFET in this work. The wide applicability of this methodology is helpful to future reliability/variability-aware circuit design in nano-CMOS technology.

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration on bulk substrate. For high-volume production, the variability of C-TFETs are experimentally investigated, demonstrating an intrinsic trade-off between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs, which is mainly impacted by the band-to-band tunneling generation area. By new TFET device design, improved performance and variability simultaneously are experimentally achieved, and circuit-level implementation shows significant operation speed enhancement (up to 93%) and energy reduction (by 66%) at VDD of 0.4V, as well as remarkably suppressed variation, indicating its great potential for ultralow-power applications.

New understanding of state-loss in complex RTN: Statistical experimental study, trap interaction models, and impact on circuits

In this paper, the statistical characteristics of complex RTN (both DC and AC) are experimentally studied for the first time, rather than limited case-by-case studies. It is found that, over 50% of RTN-states predicted by conventional theory are lost in actual complex RTN statistics. Based on the mechanisms of non-negligible trap interactions, new models are proposed, which successfully interpret this state-loss behavior, as well as the different complex RTN characteristics in SiON and high-κ devices. The circuit-level study also indicates that, predicting circuit stability would have large errors if not taking into account the trap interactions and RTN state-loss. The results are helpful for the robust circuit design against RTN.

New observations on complex RTN in scaled high-κ/metal-gate MOSFETs — The role of defect coupling under DC/AC condition

The coupling effect between multi-traps in complex RTN is experimentally studied in scaled high-κ/metal-gate MOSFETs for the first time. By using extended STR method, the narrow “test window” of complex RTN is successfully expanded to full VG swing. Evident defect coupling can be observed in both RTN amplitude and time constants. Interesting nonmonotonic bias-dependence of defect coupling is found, which is due to two competitive mechanisms of Coulomb repulsion and channel percolation conduction. The decreased defect coupling is observed with increasing AC frequency. Based on the new observations on complex RTN, its impacts on the circuit stability are also evaluated, which show an underestimation of the transient performance if not considering defect coupling. The results are helpful for future robust circuit design against RTN.

Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization — New findings on the layout dependent aging effects

In this paper, a new class of layout dependent effects (LDE)-the time-dependent layout dependency due to device aging, is reported for the first time. The BTI and HCI degradation in nanoscale HKMG devices are experimentally found to be sensitive to layout configurations, even biased at the same stress condition. This new effect of layout dependent aging (LDA) can significantly mess the circuit design, which conventionally only includes the static LDE modeled for time-zero performance. Further studies at circuit level indicate that, for resilient device-circuit-layout co-design, especially to ensure enough design margin near the end of life, LDA cannot be neglected. The results are helpful to guide the cross-layer technology/design co-optimization.

DTMOS mode as an effective solution of RTN suppression for robust device/circuit co-design

In this paper, using DTMOS as an effective solution of RTN suppression without device/circuit performance penalty is proposed and demonstrated for the first time, with experimental verification and circuit analysis. The experiments show that RTN amplitude is greatly reduced in DTMOS mode, which is even better than the body-biasing technique of FBB, due to the efficient dynamic modulation mechanism. Circuit stability and performance degradation induced by RTN are much improved in the design using DTMOS. New characteristics of RTN physics in DTMOS are also observed and studied in detail. The results are helpful to the robust and reliable device/circuit co-design in future nano-CMOS technology.

Neutron-Ser Modeling & Simulation for 0.181,1,M Cmos Technology

This paper presents a new and physical modeling approach for neutron SER with excellent accuracy demonstrated on SRAMs fabricated using 0.18µm CMOS technology. The SER contribution of each type of recoil ion and a fast roll-off behavior of neutron SER for high QCRIT nodes are reported for the first time.