Shian-Ru Lin

CCM/GM Relative Skip Energy Control and Bidirectional Dynamic Slope Compensation in a Single-Inductor Multiple-Output DC–DC Converter for Wearable Device Power Solution

Compact size wearable devices require multiple supplies with relative large loading difference, which causes serious cross regulation, large ripple, and oscillation in single-inductor multiple-output (SIMO) DC-DC converter. Thus, a continuous conduction mode/green mode (CCM/GM) relative skip energy control (RSEC) in SIMO is proposed for wearable device power solution. Different from the conventional absolute skip method, the RSEC eliminates unnecessary skip-induced voltage ripple and cross regulation with well regulation performance over wide load and voltage ranges. Optimization between efficiency and voltage ripple achieves low noise supply and reduced switching loss. In addition, smooth transition between CCM and GM provides high power and longer usage time in wearable devices. Furthermore, bidirectional dynamic slope compensation conquers subharmonic oscillation and avoids invalid pulses in the energy delivery operation of current-mode SIMO DC-DC converters. The test chip fabricated in the 0.18 μm CMOS process occupies 2.24 mm2 active area. Maximum output ripple, overshoot/undershoot, and cross regulation are kept below 40 mV, 27 mV, and 0.0432 mV/mA, respectively.

Single-Inductor Quad-Output Switching Converter With Priority-Scheduled Program for Fast Transient Response and Unlimited Load Range in 40 nm CMOS Technology

System-on-a-chip (SoC) applications require multiple power supply voltages with the features of low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for the single-inductor quad-output (SIQO) switching converter. This technique manages energy delivery to multiple outputs, facilitates fast transient response, and reduces cross-regulation simultaneously. Moreover, a level bypass detector (LBD) is used to overcome the limitation of significant loading differences among quad outputs in conventional designs because the PSP technique cantransfer additional energy to low-priority outputs to avoid overshoot voltage at high-priority outputs. Furthermore, voltage disturbance can be filtered out using two additional low-dropout regulators that operate as buffers cascaded at two low-priority outputs. Therefore, the SIQO converter that is fabricated in 40 nm CMOS technology satisfies the power requirements in portable electronics given its low cross-regulation of 0.2%, fast transient response of 15 μs, and an output voltage ripple that is smaller than 30 mV.

20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor

Multicore processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the VOUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔVOUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a current quantization error (CQE), which depends on the drive current of the least significant bit (LSB) switch in power MOSFET array. PVT variations produce changes in the CQE resulting in different ΔVOUT at different OPPs. This paper presents a DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation. Experimental results show that the proposed DLDO regulator achieves less than 3mV output ripple ΔVOUT, while T ranges from 0–80°C and VOUT ranges from 0.6–1V in steady state, and the transient response time is 1.3µs in case of a load step from 1mA to 201mA.

2.3 A single-inductor dual-output converter with linear-amplifier-driven cross regulation for prioritized energy-distribution control of envelope-tracking supply modulator

RF-PAs in 4G LTE mobile devices handle modulated signals with high peak-to-average power ratios (PAPRs) while maintaining linearity and power efficiency. Envelope-tracking technology increases the efficiency of an RF-PA by modulating its supply voltage proportionally to the RF signals. The function of an envelope-tracking supply modulator (ETSM) is to track the envelope information and provide the same output voltage to the RF-PA. Figure 2.3.1 shows a conventional hybrid ETSM, which is comprised of a linear amplifier (LA) and a hysteresis-controlled switching regulator (SWR). Since the ETSM is mainly battery-powered, an additional SWR is required. This paper presents a single-inductor dual-output (SIDO) converter that removes both SWRs, as illustrated in Fig. 2.3.2, to speed up the performance of the ETSM. In the past, a cross-regulation (CR) effect was recognized as one the most critical drawbacks in the conventional design with single-inductor multiple-output (SIMO) converters, and numerous research papers have attempted to suppress CR [1,2]. In this paper, however, the proposed ETSM design, driven by the LA, makes effective use of the CR effect for achieving faster and efficient envelope tracking. Results show that, at a switching frequency of 2MHz, the proposed ETSM can deliver up to 2W of average output power with an efficiency of 82%.

A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction

A buck power factor correction (PFC) converter operating in continuous conduction mode (CCM) is influenced by the dead zone, which introduces distortion related to the input line voltage. Such phenomenon limits the maximum power factor (PF) and the minimum total harmonic distortion (THD) achievable. By deriving a methodology to achieve predictive line voltage reconstruction (PLVR), the influence of the dead zone is mitigated. With the prediction of quadratic sinusoidal current modulation (PS2CM), the line current is shaped into sinusoid waveform that is in-phase with input line voltage, crucial for. Consequently, the proposed CCM buck PFC can achieve high PF, low THD, and efficiency simultaneously. A test chip was fabricated in 0.5-μm Bipolar-CMOS-DMOS (BCD) process. The experimental results show a peak PF of 0.95 and a peak efficiency of 98% at 110 Vac.

A Low-THD Class-D Audio Amplifier With Dual-Level Dual-Phase Carrier Pulsewidth Modulation

In this paper, a class-D audio amplifier which combines the advantages of the phase-shifted carrier pulsewidth modulation (PWM) and the multiple-level carrier PWM is proposed with a dual-level dual-phase carrier (DLDPC) PWM. The proposed closed-loop amplifier includes a second-order integrator and a DLDPC triangular wave generator. Two sets of 180° out-of-phase triangular waves are used as carriers, and each set has its respective offset voltage level with nonoverlapping amplitude. By performing the double Fourier analysis, it can be found that the linearity can be enhanced and the distortion can be reduced with the proposed modulation. Experimental results show that the proposed fully differential DLDPC PWM class-D audio amplifier features a total harmonic distortion lower than 0.01% with an output voltage swing of ±5 V.

A digital reverse current self-calibration technique in 90% high efficiency rectified power supply for near field communication through magnetic field induction

It is crucial in near field communication (NFC) controllers for power source transferred from mutual induction of coils when the devices are battery-off. NFC devices can be operated at the condition of low battery or even battery-off due to the requirement of payment any time. Thus, the proposed wireless power transfer (WPT) power supply can have high efficiency due to the remove of reverse leakage current by the digital reverse current self-calibration (DRCS). NFC standards including A, B, and F can be continuously supplied by the WPT supply system. The WPT power supply with the DRCS technique was fabricated in 0.25μm CMOS process can rectify AC source from induction of magnetic field to unregulated DC voltage source and to supply power the NFC controller through low dropout regulator (LDR). Moreover, test chip achieves as high as 92% voltage conversion ratio and 89.4 % power conversion efficiency (PCE) due to reduction of unnecessary current loss.

10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response

Advanced CMOS devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage in such devices, stacked MOSFET structures with a three-level technology are commonly employed. The stacked structure can also reduce the output voltage ripple substantially. Figure 10.5.1 shows a three-level single-inductor triple-output (SITO) converter and also compares the transient response with the SITO converter without the three-level technique. The three-level topology applies three different voltages, Vin, 1/2Vin, and VSS, to the node VX. The operation mode is determined by the duty cycle, i.e., the node Vx swings between 1/2Vin and VSS when duty cycle (D < 0.5), and between 1/2Vin and Vin, otherwise (D>0.5). In state-of-the-art [1–3], the key issue of the three-level topology is how to balance the cross voltage of flying capacitor CFLY at the point of 1/2Vin. In general, the restrained output voltage ripple and the flatter inductor current (IL) slope seriously result in worse transient response and severe cross-regulation (CR) problems, respectively. Results in Figure 10.5.1 show that the three-level SITO converter achieves a smaller output voltage ripple in steady state, but it causes the problems of slower transient response time, longer recovery time, larger overshoot/undershoot, and severe CR. Thus, it is desired to develop a technique that can adjust the cross voltage of CFLY such that the three-level topology achieves higher efficiency, lower output voltage ripple, and fast transient response simultaneously.

Pseudo-Constant Switching Frequency in On-Time Controlled Buck Converter with Predicting Correction Techniques

The predicting correction technique (PCT) is proposed to achieve an adaptive on-time control for ripple-based buck converters. The switching frequency fSW variation is suppressed when the PCT technique considers complete parasitic resistances of the components and devices. Even without extra clock-controlled circuits and current sensing circuits, the buck converter operates with a nearly constant fSW over a wide load range. Parasitic resistances almost cause no influence and restriction on f_SW. Only input voltage is used to predict the adaptive on-time. Measurement results show only 0.32% in Δf_SW/f_SW and 5.7 kHz/A in Δf_SW/ΔI_LOAD in case of 1.4 A load current change and f_SW is 2.5 MHz. Consequently, a pseudo-constant f_SW with well-defined noise spectrum strongly benefits the solution of electromagnetic interference (EMI) for system-on-a-chip (SoC) applications.

A Dynamic Bootstrap Voltage Technique for a High-Efficiency Buck Converter in a Universal Serial Bus Power Delivery Device

The dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over wide ranges of load currents for high-power universal serial bus devices. The silicon area of the embedded power management with the DBV technique in the system-on-a-chip can be effectively reduced to 50% of the conventional design with a P-type high-side power MOSFET. Test chips fabricated in 0.25-μm CMOS process showed a 92% peak efficiency from 1 mA to 1 A. The maximum driving current was higher than 5 A, and the efficiency was 88%. Compared with the efficiency of the converter without the DBV technique, the efficiency of the converter with DBV technique was improved by about 28%.