Wen-Hau Yang

12.7 A 96%-efficiency and 0.5%-current-cross-regulation single-inductor multiple floating-output LED driver with 24b color resolution

Lighting flicker, a rapid and repeated change over time in the brightness of light, has long been known to cause illness in humans that ranges from headaches to seizures. Thus, [1] has specified the dimming frequency, fDIM, larger than 3kHz to achieve a no-observable-effect flicker level. State-of-the-art LED drivers employ the SIMO topology with four channels in Fig. 12.7.1, to deliver energy to each LED using the time-multiplexing (TM) control technique [2-4], in which the luminance is controlled by the dimming signals. Two major shortcomings for such approaches are: (1) Sequential dimming signals; and (2) Current cross-regulation (CCR) effects. In [2], the LED drivers with TM control result in only 9b color resolution at the dimming frequency of 1.5kHz, which may cause flicker hazard. Besides, the complete white-red-green-blue (WRGB) sequence needs a total of four switching periods to light up the 4 LEDs separately. On the other hand, due to inherent rising and falling delay of the hysteretic current control (HCC) circuit, tdr and tdf respectively, the CCR effect seriously affects the accuracy of the controller when the inductor current slope is varied. For example, with L=15μH, VIN=20V, VR=2.5V, VG=3.5V, tdr=300ns and tdf=250ns, the SIMO will result in 4% CCR between Iavg,R and Iavg,G when the average LED current is 1A. More specifically, with the same color in the sequence, voltage regulation may be disregarded when regulated constant current through the sensing resistor RSEN is used as a negative feedback control. However, when different colors are in sequence, where VO, =VR, VG, VB, or VW, are different, large voltage cross-regulation (VCR) across the RSEN occurs and so does the CCR. The CCR effects become an open question for enhancing LED current accuracy. For alleviating the CCR effect, the discontinuous conduction mode (DCM) has been applied for TM control in [3]. However, with the limited output current in DCM, low output power resulted and large output capacitors were required to suppress the VCR. In this paper, a single-inductor multiple-floating-output (SIMFO) LED driver with an average-current-correction (ACC) technique is presented. The developed ACC technique is used to alleviate the CCR effect to about 0.5%. The developed LED driver using the floating output topology offers the following salient features: (1) A complete WRGB sequence is operated in only one switching cycle; (2) All LEDs can be dimmed simultaneously and each LED can also be dimmed individually to achieve 24b color resolution at fDIM=3kHz without flicker hazard; and (3) Achieving high output power and power efficiency (96%).

20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor

Multicore processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the VOUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔVOUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a current quantization error (CQE), which depends on the drive current of the least significant bit (LSB) switch in power MOSFET array. PVT variations produce changes in the CQE resulting in different ΔVOUT at different OPPs. This paper presents a DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation. Experimental results show that the proposed DLDO regulator achieves less than 3mV output ripple ΔVOUT, while T ranges from 0–80°C and VOUT ranges from 0.6–1V in steady state, and the transient response time is 1.3µs in case of a load step from 1mA to 201mA.

95% light-load efficiency single-inductor dual-output DC-DC buck converter with synthesized waveform control technique for USB type-C

The proposed single-inductor dual-output (SIDO) converter can provide wide range in duty ratio control to convert input voltage 5-20V to dual output voltages 3.3V and 1.2V when its switching frequency is raised to 10MHz for compact size solution. The proposed synthesized waveform control (SWC) technique can emulate the inductor current without being affected by switching noise. Thus, the minimum allowable duty ratio can be lowered to 6% to meet the requirement of USB-C in one-stage low duty ratio conversion. Moreover, the switching frequency is dynamically decreased by the derived DC loading information from the SWC technique. Not only the output power MOSFET but also the main power MOSFET switch in a load-dependent switching frequency for power saving. 67% more power reduction can be obtained. 95% and 83% efficiency are achieved at light and heavy loads, respectively, when the silicon is limited within 1400μm*1350μm.

A digital reverse current self-calibration technique in 90% high efficiency rectified power supply for near field communication through magnetic field induction

It is crucial in near field communication (NFC) controllers for power source transferred from mutual induction of coils when the devices are battery-off. NFC devices can be operated at the condition of low battery or even battery-off due to the requirement of payment any time. Thus, the proposed wireless power transfer (WPT) power supply can have high efficiency due to the remove of reverse leakage current by the digital reverse current self-calibration (DRCS). NFC standards including A, B, and F can be continuously supplied by the WPT supply system. The WPT power supply with the DRCS technique was fabricated in 0.25μm CMOS process can rectify AC source from induction of magnetic field to unregulated DC voltage source and to supply power the NFC controller through low dropout regulator (LDR). Moreover, test chip achieves as high as 92% voltage conversion ratio and 89.4 % power conversion efficiency (PCE) due to reduction of unnecessary current loss.

10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response

Advanced CMOS devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage in such devices, stacked MOSFET structures with a three-level technology are commonly employed. The stacked structure can also reduce the output voltage ripple substantially. Figure 10.5.1 shows a three-level single-inductor triple-output (SITO) converter and also compares the transient response with the SITO converter without the three-level technique. The three-level topology applies three different voltages, Vin, 1/2Vin, and VSS, to the node VX. The operation mode is determined by the duty cycle, i.e., the node Vx swings between 1/2Vin and VSS when duty cycle (D < 0.5), and between 1/2Vin and Vin, otherwise (D>0.5). In state-of-the-art [1–3], the key issue of the three-level topology is how to balance the cross voltage of flying capacitor CFLY at the point of 1/2Vin. In general, the restrained output voltage ripple and the flatter inductor current (IL) slope seriously result in worse transient response and severe cross-regulation (CR) problems, respectively. Results in Figure 10.5.1 show that the three-level SITO converter achieves a smaller output voltage ripple in steady state, but it causes the problems of slower transient response time, longer recovery time, larger overshoot/undershoot, and severe CR. Thus, it is desired to develop a technique that can adjust the cross voltage of CFLY such that the three-level topology achieves higher efficiency, lower output voltage ripple, and fast transient response simultaneously.

A low quiescent current and cross regulation single-inductor dual-output converter with stacking MOSFET driving technique

The stacking MOSFET structure composed of low-voltage devices suffers from deteriorated transient response or large footprint area when capacitor-free or dominant pole compensation low dropout (LDO) regulator biases the driver. Due to self-stabilized feature, the proposed stacking MOSFET driving (SMD) technique effectively drives the power stage and greatly reduces noise interference from the noisy node to achieve low cross regulation (CR) in the single-inductor dual-output (SIDO) converter. Moreover, two inherent low dropout (LDO) regulators in the SMD technique completely regulate two outputs with low quiescent current at no load condition. Experimental results show the tested chip fabricated in 0.25μm process with low cross regulation of 0.015mV/mA and ultra-low quiescent current of 5μA at no load condition.

Unsymmetrical parallel switched-capacitor (UP-SC) regulator with fast searching optimum ratio technique

Different from conventional multiphase switched-capacitor (SC) DC-DC converters, the proposed unsymmetrical parallel switched-capacitor (UP-SC) regulator provides more controllable input variables to increase available conversion ratios for improved load regulation. Even under higher conversion ratio numbers, the UP-SC regulator uses the fast searching optimum ratio (FSOR) technique to search the destined ratio rapidly and to reduce the transient recovery time. Experimental results show the test chip fabricated in 0.25μm CMOS process increases the ratio number to 187 and 2389 in 3-stage and 4-stage SC regulators, respectively. Transient recovery time reduces from 26μ8 to 1.5μ8 in case of 7mA load current step.

93% Efficiency and 0.99 power factor in pseudo-linear LED driver

The proposed pseudo-linear LED driver can effectively solve the serious flicker in conventional linear LED driver (LLD). Besides, it has good electromagnetic interference (EMI) performance similar to that in conventional LLD at high AC input voltage. In the meanwhile, it has high power factor (PF) similar to boost switching regulator (SWR) LED driver at low AC input voltage. Furthermore, owing to the combination of line filter and the active full bridge rectifier, the pseudo-linear LED driver has a compact solution and high efficiency. The test chip was fabricated in 0.5μm 500V LDMOS process. Experimental results show 93% high efficiency, 6% total harmonic distortion (THD), and 0.99 PF at the power of 7W.

Suppressing output overshoot voltage technique with 47.1mW/μs power-recycling rate and 93% peak efficiency DC-DC converter for multi-core processors.

Conversion efficiency degrades in case of heavy-to-light loading change since state-of-art overshoot reduction techniques simply dissipate redundant energy at the output of buck DC-DC converter. Thus, the proposed dual-mode ripple-recovered compensator (D-RRC) and multi-phase suppressing output overshoot voltage (MP-SOOV) technique uses 33nH bondwire inductance to recycle energy and provides 47.1mW/μs ultra-fast power-recycling rate to suppress overshoot voltage from 507mV to 95mV with 81.3% improvement when load changes from 1.7A to 0.3A. Experimental results show 93% high efficiency and highspeed operation with only tens of nano second on-time period.