Shigeru Kuhara

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator

This 512 kw/spl times/8 b/spl times/4 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator, and a 0.4 /spl mu/m BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Circuit approaches include 1) zigzag double word-line, 2) centralized bit-line load layout, and 3) phase-locked-loop (PLL) with a multi-stage-tapped (MST) ring oscillator that generates not only a de-skewed internal clock, but also a clock-cycle-proportional pulse and a clock-edge-lookahead pulse. >

A 6 ns 1.5 V 4 Mb BiCMOS SRAM

Although BiCMOS technology has been used to realize high-speed cache memories, the unscalable 0.8 V Vbe of the bipolar makes it difficult to design 1.5 V BiCMOS circuits including bipolar sense amplifiers. Four circuits in a 0.3 /spl mu/m 4 Mb BiCMOS SRAM overcome this difficulty: (1) boost-BinMOS gates for address decoding, (2) an optimized word-boost for a highly-resistive-load memory cell, (3) a stepped-down CML cascoded bipolar sense amplifier, (4) optimum boost-voltage generator. The SRAM has 6 ns access time at a minimum supply voltage, 1.5 V.

PLL timing design techniques for large-scale, high-speed, low-power, and low-cost SRAMs

PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme employing a clock-cycle proportional pulse, (2) a clock cyclic input buffer power-cutting scheme employing a clock-edge lookahead pulse, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers. These techniques successfully contribute to the development of a 7 ns 16 Mb BiCMOS SRAM LSI.<<ETX>>