Shigeru Nakahara

Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm

This paper presents a built-in self-test (BIST) scheme, which consists of a flexible pattern generator and a practical on-macro two-dimensional redundancy analyzer, for GHz embedded SRAMs. In order to meet the system requirements and to detect a wide variety of faults or performance degradation resulting from recent technology advances, the microcode-based pattern generator can generate flexible patterns. A practical new repair algorithm for the Finite State Machine (FSM)-based on-macro redundancy analyzer is also presented. It can be implemented with simple hardware and can show fairly good performance compared with conventional software-based algorithms.

Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core

Describes novel schemes developed to meet the demand for a reusable embedded SRAM core for application to a variety of SOC designs. PAS optimizes sense-amplifier activation timing by using the combination of a program and automatic control. MRAD minimizes timing-overhead by reducing the fluctuation of path-to-path delay. These schemes experimentally demonstrated a wide-operation range of 0.5 to 1.4 V and an access time of 600 ps.

A design for a minimum Hamming-distance search using asynchronous digital techniques

An approach for a completely static and digital implementation of a minimum Hamming-distance search is presented in this paper. A newly developed associative memory performs the search operation by executing a bubble sort operation for a binary data, which we call a bubble shift, with the assistance of three kinds of replica signals generated from a replica word and bit scheme. The bubble shift operation is achieved with a bit swap cell which swaps its own value with neighboring cells asynchronously and in parallel. This concentration of asynchronous techniques used in the memory allows for a 35-ns search-time for a 64 word /spl times/ 128 bit macro with 0.13-/spl mu/m 7-layer CMOS process.

A digital circuit for a minimum distance search using an asynchronous bubble shift memory

The architecture described allows a fully digital circuit to search for the minimum Hamming distance. It compares favorably with prior approaches in its robustness and short design time. A concentration of asynchronous circuit techniques allows a 35 ns search time of 64 entry/spl times/128 bit data with a 0.13 /spl mu/m 5M CMOS process.