Kazuo Kanetani

A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM

High-speed, high-density 4-4.5Mb CMOS cache SRAMs do not have speed comparable to that of a 4.5Mb BiCMOS SRAM. This 4.5Mb CMOS SRAM has access time equivalent to that of a BiCMOS SRAM. Key techniques for achieving this speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array.

High-speed sensing techniques for ultrahigh-speed SRAMs

Two high-speed sensing techniques suitable for ultrahigh-speed SRAMs are proposed. These techniques can reduce a 64-kb SRAM access time to 71 approximately 89% of that of conventional high-speed bipolar SRAMs. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAMs for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 approximately 43% of that of conventional cells. A 64-kb SRAM fabricated with one of the sensing techniques using 0.5- mu m BiCMOS technology achieved a 1.5-ns access time with a 78- mu m/sup 2/ memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAMs, which have been used as cache and control memories of mainframe computers. >

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory cells has been developed using 0.3-/spl mu/m BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAMs, which have been used as cache and control storages in mainframe computers. >

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers. >

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.

An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

An experimental soft-error-immune 64-kbit 3-ns ECL RAM has been developed. This high performance is achieved by using a soft-error-immune switched-load-resistor memory cell with clamp transistors, an upward-transistor decoder utilizing a SIdewall-base COntact Structure (SICOS) upward transistor for the AND gate, a Darlington word driver with advanced discharge circuits, and 0.8- mu m SICOS technology. High-load and low-load resistors in this new memory cell are formed by using double-layer polysilicon for the base and emitter electrodes in the SICOS structure. This results in a small cell size (498 mu m/sup 2/) and a reasonable chip size (85.8 mm/sup 2/). An accelerated soft-error test using americium alpha source shows that the new 64-kbit RAM has sufficient soft-error immunity, in spite of its small cell capacitance which is about one third that of conventional RAMs. In addition to the new memory cell, the upward-transistor decoder and the Darlington word driver with advanced discharge circuits make it possible to realize a high-speed, large-capacity bipolar RAM, while maintaining soft-error immunity. >

An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM

An experimental soft-error immune 64-kb 3-ns emitter couple logic (ECL) random access memory (RAM) has been developed. Its key factors are: a soft-error immune memory cell, an upward transistor decoder, a Darlington word driver with advanced discharge circuits, and 0.8 mu m SICOS technology. To reduce the memory cell size, double-layer polysilicon is used for high and low load-resistor. These double layers of polysilicon are essential in realizing the memory cell size of 498 mu m/sup 2/.<<ETX>>

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz

This paper describes power reduction circuit techniques in an ultra-high-speed emitter-coupled logic (ECL)-CMOS SRAM. Introduction of a 0.25-/spl mu/m MOS transistor allows a Y decoder and a bit-line driver to be composed of CMOS circuits, resulting in a power reduction of 34%. Moreover, a variable-impedance load has been proposed to reduce cycle time. A 1-Mb ECL-CMOS SRAM was developed by using these circuit techniques and 0.2-/spl mu/m BiCMOS technology. The fabricated SRAM has an ultrafast access time of 550 ps and a high operating frequency of 900 MHz with a power dissipation of 43 W.

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM

An ultrahigh-speed 1-Mb emitter-coupled logic (ECL)-CMOS SRAM with 550-ps clock-access time, 900-MHz operating frequency, and 12-/spl mu/m/sup 2/ memory cells has been developed using 0.2-/spl mu/m BiCMOS technology. Three key techniques for achieving the ultrahigh speed are a BiCMOS word decoder/driver with an nMOS level-shift circuit, a sense amplifier with a voltage-clamp circuit, and a BiCMOS write circuit with a variable-impedance bitline load. The proposed word decoder/driver and sense amplifier can reduce the delay times of the circuits to 54% and 53% of those of conventional circuits. The BiCMOS write circuit can reduce the power dissipation of the circuit by 74% without sacrificing writing speed. These techniques are especially useful for realizing ultrahigh-spaced high-density SRAMs, which will be used as cache and control memories in mainframe computers.

A 3.5ns, 2W, 20mm 2 16Kb ECL bipolar RAM

THIS PAPER WILL DESCRIBE a 3.5ns ECL 16Kb bipolar RAM with a power dissipation of 2W, cell size of 4 9 5 ~ 2 and chip size of 20mm2. The most critical requirements for bipolar RAMs are high speed, low power dissipation and small chip size. Two circuit techniques are proposed to meet the foregoing criteria: ( I ) a Schottky barrier diode (SBD) decoder combined with an address buffer and a latch circuit having three-level VBB; ( 2 ) a Darlington word driver having double-stage discharge circuits. The SBD decoder circuit combined with the address buffer and latch circuits is shown in Figure 1. The decoder reduces access time by 20% compared to a conventional multi-emitter decoder, because the parasitic capacitance CDE at the decoder output can be reduced by about 65%. The lower capacitance is due to the small area and small junction capacitance per unit area. Two SBDs have been connected in series to obtain a forward voltage higher than a base-emitter voltage VBE of the transistor QE. This enables the decoder to be completely cut off, insuring a sufficiently high level at the decoder output. To realize even higher speeds at the system level, an on-chip buffer and latch must be combined with the SBD decoder. However, a simple combination of the conventional address buffer and latch using a series gate’ and SBD decoder cannot be used because of transistor (Ql /Q2) saturation under a given supply voltage (-5.2V); Figure 1. To overcome this problem, an address buffer and latch with a threelevel VBB, also shown in Figure 1, is proposed. The latch operation can be performed by the three-level VBB without any loss in speed. Until the clock CLK turns on, the VBB generator offers a VBB in accordance with the previous address input (ADR) levels as shown in Figure 2. That is, the VBB is set to a lower (higher) level than any address input level for high (low) level address input. Therefore, the outputs of the address buffer are held high or low regardless of the following address input changes. When the clock CLK turns on at to, the output of the VBB generator is switched to a standard VBB level for a 10K or lOOK logic family. Thus, the outputs of the address buffers can be changed in accordance with the address inputs. This address information is retained when the CLK turns off again. Figure 3 shows a Darlington word driver using double-stage discharge circuits connected to each of the transistor emitters. Sufficient discharge currents are provided (I1 = 2mA, I2 = 6mA) without a significant voltage drop on the word line. Conventional delayed discharge circuits are also used at the end of the word lines to increase the cell margin. Since both discharge circuits are delay-type, it is possible to maintain a high current after the word line voltage switches to a low level. The driver reduces further the access time by about 15Yc. The increase in power dissipation is negligibly small in spite of the high