Kunihiko Yamaguchi

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect

This paper describes an investigation of cosmic-ray-induced multicell error behavior in SRAMs. A combination of device- and circuit-level simulation was used to show that a parasitic bipolar effect is responsible for such errors, and the underlying mechanism is what we call a battery effect. We have also demonstrated, for the first time, that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well taps (Nc). The results are used as the basis of an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multicell errors. The proposed guideline simply states that the allocation of memory cells to addresses should be based on consideration of the Nc. The architecture in its form reduces the soft error rate of an SRAM with Nc=16 by 88%.

A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM

High-speed, high-density 4-4.5Mb CMOS cache SRAMs do not have speed comparable to that of a 4.5Mb BiCMOS SRAM. This 4.5Mb CMOS SRAM has access time equivalent to that of a BiCMOS SRAM. Key techniques for achieving this speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array.

High-speed sensing techniques for ultrahigh-speed SRAMs

Two high-speed sensing techniques suitable for ultrahigh-speed SRAMs are proposed. These techniques can reduce a 64-kb SRAM access time to 71 approximately 89% of that of conventional high-speed bipolar SRAMs. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAMs for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 approximately 43% of that of conventional cells. A 64-kb SRAM fabricated with one of the sensing techniques using 0.5- mu m BiCMOS technology achieved a 1.5-ns access time with a 78- mu m/sup 2/ memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAMs, which have been used as cache and control memories of mainframe computers. >

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory cells has been developed using 0.3-/spl mu/m BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAMs, which have been used as cache and control storages in mainframe computers. >

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers. >

A 6ns 4Kb bipolar RAM using switched load resistor memory cell

current memory cell operation and fast word line switching are the keys to fast, large capacity (above 4Kb) bipolar RAMs. However, it is difficult to achieve this performance in large capacity memories with conventional parallel diode memory cells’. This problem was overcome with a switched load resistor memory cell; Figure 1. At standby, the load resistance of the memory cell is high ( R ~ ~ 1 5 0 k f i ) . When the memory cell is selected, a read current flows through Schottky diodes, and consequently, the load resistance is automatically switched to a lower value ( R ~ = 2 5 0 f i ) . This load resistor switching affords a large read current (2mA), smaller standby current (4pA) and a fast memory cell readtime of 0.511s. Power dissipation does not increase in spite of the large read current, because the read current is directed only to the selected memory cell by the use of a switched read current It has been found by computer simulation that large-read-

A 0.9-ns-access, 700-MHz SRAM macro using a configurable organization technique with an automatic timing adjuster

The key to improving the performance of a single chip processor is to incorporate many varieties of SRAM macros with a word/bit-flexible configuration. To improve the performance even more, a configurable organization technique featuring a leaf cell design is proposed. In applying the technique, the timing design became too critical for the high-performance processor. An automatic timing adjuster is thus proposed to adjust the sense amplifier activation timing automatically in each organization. In addition, a low Vth MOS transistor is applied in order to improve access time. To overcome the increase in current leakage due to a low Vth, a back-bias control circuit is also proposed. These techniques in conjunction with a 0.25 /spl mu/m CMOS process make it possible to achieve a 0.9 ns access, 700 MHz SRAM macro.

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.

An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

An experimental soft-error-immune 64-kbit 3-ns ECL RAM has been developed. This high performance is achieved by using a soft-error-immune switched-load-resistor memory cell with clamp transistors, an upward-transistor decoder utilizing a SIdewall-base COntact Structure (SICOS) upward transistor for the AND gate, a Darlington word driver with advanced discharge circuits, and 0.8- mu m SICOS technology. High-load and low-load resistors in this new memory cell are formed by using double-layer polysilicon for the base and emitter electrodes in the SICOS structure. This results in a small cell size (498 mu m/sup 2/) and a reasonable chip size (85.8 mm/sup 2/). An accelerated soft-error test using americium alpha source shows that the new 64-kbit RAM has sufficient soft-error immunity, in spite of its small cell capacitance which is about one third that of conventional RAMs. In addition to the new memory cell, the upward-transistor decoder and the Darlington word driver with advanced discharge circuits make it possible to realize a high-speed, large-capacity bipolar RAM, while maintaining soft-error immunity. >

A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

An LSI device incorporating a 36-kb RAM and a 1k-gate logic array and using a 0.8- mu m sidewall base contact structure (SICOS) transistor process and four-layer metallization, is described. RAM and peripheral logic have been included in one chip to reduce input/output delay and interconnection delay between the RAM and logic. The chip layout is shown together with the circuit schematic of the RAM macro. RAM address access waveforms are shown along with the waveform of a 21-stage ring oscillator. Major device characteristics are summarized.<<ETX>>