Shih-Chung Lee

A 56-nm CMOS 99-

A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the worlds first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum2 per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size

{\hbox {mm}}^{2}

Today NAND Flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. Figure 13.6.1 shows the memory-density trend since 2003. To satisfy the market demand for lower cost per bit and higher density nonvolatile memory, in addition to technology scaling, 2b/cell MLC technology was introduced. Recently, MLC NAND flash memories with more than 2b/cell [1,2] have been reported.