Shih-Lun Chen

Implementation and prototyping of a complex multi-project system-on-a-chip

A silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. A multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with eleven SoC projects sharing the common platform. The total silicon area is about 37.97mm2 in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area 129.39mm2 by implementing these projects separately, the results show that there are 91.42mm2 silicon areas reduced by the MP-SoC platform. In order to verify MP-SoC through silicon prototyping, a system modeling and hardware/ software co-design virtual platform were implemented. A configurable SoC prototyping system, namely CONCORD, is also created as a verification platform for emulating the hardware of MP-SoC before chip being taped out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems.

A novel methodology for Multi-Project System-on-a-Chip

In this paper, a novel silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. For integrating heterogeneous SoC projects into a single chip, the current SoC methodology is insufficient due to the complexity of MP-SoC. In order to improve the robustness of MP-SoC design and verification, a new design flow was developed. It consists of a virtual platform, a logical implementation, a rapid prototyping platform, a physical implementation, and testing stages. The virtual platform is a system modeling and hardware/software co-design system by using electronic system level (ESL). VIP system is adopted for the AMBA-compliant check of the interfaces of the MP-SoC. In addition, STEAC and DFT were used to facilitate MP-SoC testing integration. The rapid prototyping platform called “CONCORD” which has characteristics of connection flexibility, modularization, and consistence architecture for emulating the hardware of MP-SoC before chip being taped out. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with ten SoC projects sharing the common platform. The total silicon area is about 37.97mm2 in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area 129.39mm2 by implementing these projects separately, the results show that there are 91.42 mm2 or 70.6 % silicon area reduced by this novel silicon prototyping methodology.

A configurable prototyping platform for multi-project system-on-a-chip

This paper presents a configurable CONCORD platform for Multi-Project System-on-a-Chip (MP-SoC) implementation. The multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. A configurable SoC prototyping platform CONCORD is created as a verification platform for emulating the hardware of MP-SoC before chip being taped out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with eleven SoC projects sharing the common platform. The experimental results show that 91.42 mm2 silicon areas reduced by the MP-SoC methodology.

An efficient memory controller for 3D heterogeneous integration platform

This paper presents an efficient memory controller VLSI design for integrating a 3D heterogeneous MorPACK system. The MorPACK system is a platform-based integration system and its structure is stacked by heterogeneous sub-modules. In order to reduce fabrication cost and increase the flexibility of memory extension, a novel multimode memory controller is proposed in this paper. The multimode memory controller supports NOR flash, NAND flash, and SDRAM memory with a wide capacity range. Hence, different MorPACK systems for various applications can be integrated by using the same multi-mode memory controller to satisfy different memory requirements. To demonstrate the effectiveness of the proposed methodology, three single-mode memory controllers are also implemented. With the technique of sharing one system-side signals, the pin count can reduce 41.9% while the pin count can reduce 19.2% by applying the technique of sharing memory-side signals. The total silicon area of single-mode memory controllers is about 6.83-mm2 in the TSMC 90 nm CMOS generic logic process technology. Compared with the total chip area 3.1-mm2 of our proposed multi-mode memory controller, the results show that there are 54.7 % fabrication cost reduced.

A study on thermal analysis for 3D heterogenous embedded system integration platform MorPACK

This paper presents a thermal analysis result for a 3D heterogeneous embedded system integration MorPACK (morphing package) platform. The MorPACK platform is stacked by heterogeneous submodules composed of bare dies, a substrate, connection bridges, and solder balls. Since the tiny, heterogeneous and integrable characteristics of MorPACK platform, it needs to be fabricated in high-density and laminar structure. The cooling ability of forced convection is restricted. This study presents an important characteristic for this 3D structure and two indications to optimize thermal solution for MorPACK structure. The characteristic shows the lowest layer owns the best cooling condition, so the bare die chip with highest power consumption should be placed on the lowest layer. It achieves cooling a 0.45-W consuming chip by 12-degree more than it put on the top layer. One of the indications shows the vertical thermal conductivity can be improved by filling up whole MorPACK with mold material. This skill efficiently cools down the 0.45-W consuming chip by 10-degree more than non-filled-up structure. The other indication shows removing the connection bridges and cutting out the substrate to make a room space for chip placement. With result shown, 50 % height and volume of MorPACK can be minimized and also reduce thermal resistance in out-plan direction.

A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification

This paper proposes a packet-based verification platform with serial link interface for emulating the hardware of the heterogeneous IPs before tape out. With the serial link interface Serializer/Deserializer (SerDes) added between IPs, significant amount of pin counts can be reduced in the platform. An adapter is inserted between IP and SerDes to convert parallel bus into packets and handle the handshaking. Under our proposed adapter architecture and handshaking scheme, the limitation on the number of the master adapter is eliminated compared with Bus-based Advanced High-performance Bus (AHB) architecture. Simulation results show the data transfer through our proposed architecture works correctly without the limitation on the number of masters. With the proposed adapter and SerDes architecture, the number of required signals in the interconnect is reduced from 79 to two for the AHB bus.