Shinji Satoh

A 0.67 /spl mu/m/sup 2/ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs

An ultra high-density NAND-structured memory cell, using a new Self-Aligned Shallow Trench Isolation (SA-STI) technology, has been developed for a high performance and low bit cost 256 Mbit flash EEPROM. The SA-STI technology results in an extremely small cell size of 0.67 /spl mu/m/sup 2/ per bit, 67% of the smallest flash memory cell reported so far, by using a 0.35 /spl mu/m technology. The key technologies to realize a small cell size are (1) 0.4 um width Shallow Trench Isolation (STI) to isolate neighboring bits and (2) a floating gate that is self-aligned with the STI, eliminating the floating-gate wings. Even though the floating-gate wings are eliminated, a high coupling ratio of 0.65 can be obtained by using the side-walls of the floating gate to increase the coupling ratio. Using this self-aligned structure. A reliable tunnel oxide can be obtained because the floating gate does not overlap the trench corners, so enhanced tunneling at the trench corner is avoided. Therefore, the SA-STI cell combines a low bit cost with a high performance and a high reliability, such as the fast programming (0.2 /spl mu/sec/byte), fast erasing (2 msec), good write/erase endurance (>10/sup 6/ cycles), and excellent read disturb characteristics(>10 years). This paper describes the process technologies and the device performance of the SA-STI cell, which can be used to realize NAND EEPROMs of 256 Mbit and beyond.<<ETX>>

Stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (/spl Delta/V/sub th/) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high-temperature (125/spl deg/C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30/spl deg/C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures.

A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance

This paper describes the key technology to realize a scaled NAND EEPROM with the minimized program disturbance. It has been clarified for the first time that the program disturbance caused by neighboring cells is drastically improved by reducing the field implantation dose. The limitation of conventional LOGOS width is estimated to be about 0.56 /spl mu/m. Moreover, a careful device design and an optimization of the bottom implantation are essential in an advanced STI cell.

A novel gate-offset NAND cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memories

This paper describes a novel scaled and low-voltage-operation NAND EEPROM technology with a G_ate-O_ffset NAND C_ell (GOC-NAND), which is free from program disturbance in a self-boosted program. In GOC-NAND, novel source/drain engineering is introduced for the first time. The program disturbance is decreased by two decades of magnitude in 0.1 /spl mu/m generation, without area penalty and additional process steps. Furthermore, the program disturbance is not increased by scaling and low voltage operation. Therefore, GOC-NAND is indispensable technology for gigabit-scaled NAND EEPROMs.

A source-line programming scheme for low voltage operation NAND flash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 /spl mu/s/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme.

A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND flash memories

This paper describes a novel Channel Boost Capacitance (CBC) cell technology suitable for highly scaled and fast-programming NAND flash memories. The CBC cell realizes a very high channel boost ratio in self-boosted programming without additional gate control, and drastically improves program disturbance with decreasing design rule, especially less than 0.2 /spl mu/m-rule. This memory cell is essential for realizing highly scaled, and fast-progamming NAND flash memories of 4 Gbit and beyond.

Stress induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics

This paper describes the characteristics of the stress induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items are newly observed. First, the threshold voltage shift (/spl Delta/Vth) of the memory cell under gate stress condition (read disturb condition) consists of two regions, a decay region and a steady state region. The decay region is due to both the initial trapping or detrapping of carriers in the tunnel oxide and the decay of the stress induced leakage current of the tunnel oxide. The steady state region is determined by the saturation of the stress induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high temperature (125/spl deg/C) write/erase operation degrades the steady state region characteristics in comparison with room temperature (30/spl deg/C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures.