Takaaki Fuchikami

A Wearable Healthcare System With a 13.7

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

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This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 μA including 1.28- μA non-volatile MCU and 0.7- μA heartbeat detector.

A Noise Tolerant ECG Processor

This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector

A ferroelectric-based (FE-based) non-volatile flip-flop (NWF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size while maintaining a wide read voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year, 85°C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6/fS for 10-year data retention, and 170ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. Applying the proposed circuitry in 32bit CPU of a vital sensor LSI, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr, Ti)O3(PZT) thin films.

A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system

This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise tolerant instantaneous heart rate (IHR) monitor. The novelty of this work is the combination of the non-volatile MCU for normally-off computing and a noise-tolerant-QRS (heart beat) detection algorithm to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are employed. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heart beat detector employs a coarse-fine autocorrelation and a template matching technique. Accurate heart beat detection also contributes system level power reduction because the active ratio of ADC and digital block can be reduced using a heart beat prediction. Then, at least 25% active time can be reduced. Measurement results show the fully integrated ECG-SoC consumes 6.14μA including 1.28-μA nonvolatile MCU and 0.7-μA heart rate extractor.

A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability

Novel solid-state spatial light modulator (SLM) is developed by using an electro-optic thin film technology. The use of sol-gel technique makes it possible to fabricate optically smooth 800nm-thick lead zirconate titanate (PZT) films. It shows large electro-optic effects Deltan=0.02 with the fastest switching response of 12ns that have ever been reported. The prototype 180times180 SLM array on 5mmtimes5mm-size chip demonstrates 2-dimensional displays with the three primary colors

A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems

This paper presents a low-power wearable biosignal monitoring system. The proposed system can communicate with smartphones using Near Field Communication (NFC) to check vital signs easily at any time. It comprises a battery, electrodes, a triaxial accelerometer IC, an NFC tag IC, and a biosignal processor LSI. The proposed biosignal processor LSI, fabricated using a 130-nm CMOS process, comprises heart rate monitoring circuits, a 32-kbyte ferroelectric random access memory (FeRAM), an accelerometer interface, and an NFC interface. The proposed system consumes 38.1 μA for logging application at 32-kHz operating frequency, with 3.0-V supply voltage.

Novel solid-state spatial light modulator on integrated circuits for high-speed application with electro-optic thin film

Novel solid-state spatial light modulator (SLM) is developed. An electro-optic spatial ligNovel solid-state spatial light modulator (SLM) is developed. An electro-optic spatial light modulator (EOSLM) has advantages of high-speed operation, solid-state structure and easy integration with silicon LSIs in comparison with liquid crystal displays (LCD) and micro-electro-mechanical system (MEMS) displays. We propose a kind of Fabry-Perot type planer optical pixel to achieve high optical efficiency and high aperture ratio. The use of sol-gel technique makes it possible to fabricate optically smooth 800nm-fhick lead zirconate titanate (PZT) films, which results in sufficient transparency for the three primary colors of visible light. The large electro-optic effects of Deltan=0.026 is confirmed, and the optical switching response of 7ns is fastest compared with that have ever been reported. The prototype 180x180 SLM chip, which includes pixel driver circuits, is fabricated and successfully demonstrated. ht modulator (EOSLM) has advantages of high-speed operation, solid-state structure and easy integration with silicon LSIs in comparison with liquid crystal displays (LCD) and micro-electro-mechanical system (MEMS) displays. We propose a kind of Fabry-Perot type planer optical pixel to achieve high optical efficiency and high aperture ratio. The use of sol-gel technique makes it possible to fabricate optically smooth 800nm-fhick lead zirconate titanate (PZT) films, which results in sufficient transparency for the three primary colors of visible light. The large electro-optic effects of Deltan=0.026 is confirmed, and the optical switching response of 7ns is fastest compared with that have ever been reported. The prototype 180x180 SLM chip, which includes pixel driver circuits, is fabricated and successfully demonstrated.

A 38 μA wearable biosignal monitoring system with near field communication

The low-power FE-based NVFF is developed by reduction of FE capacitor size. In the proposed NVFF, coupled FE capacitors with complementary data storage are introduced. The use of complementarily stored data in coupled FE capacitors achieves 88% FE capacitor size reduction while maintaining a wide read voltage margin of 240 mV (minimum) at 1.5 V, which results in 2.4 pJ low access energy with 10-year, 85°C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 μs for 10-year data retention, and 170 ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. As a design example, the proposed NVFF is applied to 32-bit CPU in a vital sensor LSI for wearable healthcare applications. The vital sensor LSI consists of an electrocardiogram (ECG) sensor, the 32-bit CPU core with NVFF, and a 16-Kbyte FE-based non-volatile memory (NVRAM) for data and instruction. Because the frequency range of vital signals is low, both the standby power reduction and sleep time maximization is important to system level power reduction. Its standby current can be cut when the state of CPU core transits to deep sleep. Then the data in the memory and register values of CPU core in the NVFF are stored sequentially to ferroelectric capacitors. The implementation result demonstrates that 87% of total power dissipation during measurement of the heart rate can be reduced with 64% area overhead using 130-nm CMOS with Pb(Zr, Ti)O3(PZT) thin films.

Novel Solid-State Spatial Light Modulator on Integrated Circuits for High-Speed Applications with Electro-Optic Thin Film

This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line non-precharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plate-line charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.