Shinya Kajiyama

The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories

This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory. We acquired large-scale data of Vth fluctuation and confirm the existence of the tail bits generated by RTS. The amount of Vth broadening due to the tail bits becomes larger as the scaling advances, and reaches to more than 0.3 V in 45-nm node. Thus the RTS becomes prominent issue for the design of multilevel flash memory in 45-nm node and beyond

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.

A 300 MHz embedded flash memory with pipeline architecture and offset-free sense amplifiers for dual-core automotive microcontrollers

We propose a novel 300 MHz embedded flash memory for dual-core microcontrollers targeting shared ROM architecture. One of the features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduced performance penalty due to shared ROM access conflict. The second feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch because of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and the proposed sense amplifiers achieves significant reduction in access-conflict penalties with shared ROM and enhanced performance of 32-bit RISC dual-core microcontrollers by 30%.

27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imaging

A diagnostic ultrasound (US) system transmits acoustic waves at several to tens of MHz into the human body for clinical purposes and detects the reflected waves to observe the internal organs without having a medical operation or radiation exposure. The system is composed of a main unit and probe connected via coaxial cables. The probe is very small because medical technicians laboriously grab and manipulate it for a long time. To avoid image obscurity depending on medical technicians, high-speed and high-resolution 3D/4D imaging is necessary. For this reason, several thousands of lead bulk piezoelectric material transducers (TD) need to be squeezed into the small probe. Since the number of cables is limited to several hundreds, the probe needs to include beamforming functionality and a 2D array IC [1–6], which includes thousands of US transceivers.

A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model

A design methodology optimizing constant-charge-injection programming (CCIP) for assist-gate (AG)-AND flash memories is proposed. Transient circuit simulations using an array-level model including lucky electron model (LEM) current source describing hot electron physics enables a concept design over the whole memory-string in advance of wafer manufacturing. The dynamic programming behaviors of various CCIP sequences, obtained by circuit simulations using the model is verified with the measurement results of 90-nm AG-AND flash memory, and we confirmed that the simulation results sufficiently agree with the measurement, considering the simulation results give optimum bias AG voltage approximately within 0.2V error. Then, we have applied the model to a conceptual design and have obtained optimum bit line capacitance value and CCIP sequence those are the most important issues involved in high-throughput programming for an AG-AND array.