Shogo Narukawa

Electron beam inspection of 16nm HP node EUV masks

EUV lithography (EUVL) is the most promising solution for 16nm HP node semiconductor device manufacturing and beyond. The fabrication of defect free EUV mask is one of the most challenging roadblocks to insert EUVL into high volume manufacturing (HVM). To fabricate and assure the defect free EUV masks, electron beam inspection (EBI) tool will be likely the necessary tool since optical mask inspection systems using 193nm and 199nm light are reaching a practical resolution limit around 16nm HP node EUV mask. For production use of EBI, several challenges and potential issues are expected. Firstly, required defect detection sensitivity is quite high. According to ITRS roadmap updated in 2011, the smallest defect size needed to detect is about 18nm for 15nm NAND Flash HP node EUV mask. Secondly, small pixel size is likely required to obtain the high sensitivity. Thus, it might damage Ru capped Mo/Si multilayer due to accumulated high density electron beam bombardments. It also has potential of elevation of nuisance defects and reduction of throughput. These challenges must be solved before inserting EBI system into EUV mask HVM line. In this paper, we share our initial inspection results for 16nm HP node EUV mask (64nm HP absorber pattern on the EUV mask) using an EBI system eXplore® 5400 developed by Hermes Microvision, Inc. (HMI). In particularly, defect detection sensitivity, inspectability and damage to EUV mask were assessed. As conclusions, we found that the EBI system has capability to capture 16nm defects on 64nm absorber pattern EUV mask, satisfying the sensitivity requirement of 15nm NAND Flash HP node EUV mask. Furthermore, we confirmed there is no significant damage to susceptible Ru capped Mo/Si multilayer. We also identified that low throughput and high nuisance defect rate are critical challenges needed to address for the 16nm HP node EUV mask inspection. The high nuisance defect rate could be generated by poor LWR and stitching errors during EB writing of 64nm HP resist pattern. This result suggests we need further improvements not only in the EBI inspection system but also the patterning processes for 16nm HP node EUV masks.

Mask pattern quality assurance based on lithography simulation with fine pixel SEM image

We evaluated the accuracy of the simulation based on mask edge extraction for mask pattern quality assurance. Edge extraction data were obtained from SEM images by use of TOPCON UR-6080 in which high resolution (pixel size of 2nm) and fine pixel SEM image (8000 x 8000 pixels) acquisition is possible. The repeatability of the edge extraction and its impact on wafer image simulation were studied for a normal 1D CD prediction and an edge placement error prediction. The reliability of the simulation was studied by comparing with actual experimental exposure results with an ArF scanner. In the normal 1D CD prediction, we successfully obtained good repeatability and reliability. In 65nm node, we can predict a wafer CD with the accuracy of less than 1 nm using the simulation based on mask edge extraction. In the edge placement error prediction mode, the simulation accuracy is ~5 nm including edge extraction repeatability and the uncertainty of lithography simulation model. The simulation with edge extraction more accurately predicts the resist pattern at line-end in which the actual mask pattern may be varied from the mask target (CAD) than a conventional simulation in which CAD is used as a mask pattern. This result supports the view that the wafer simulation with edge extraction is useful for mask pattern quality assurance because it can consider actual mask pattern shape.

A novel mask proximity correction software combining accuracy and reduced writing time for the manufacturing of advanced photomasks

The new generations of photomasks are seen to bring more and more challenges to the mask manufacturer. Maskshops face two conflicting requirements, namely improving pattern fidelity and reducing or at least maintaining acceptable writing time. These requirements are getting more and more challenging since pattern size continuously shrinks and data volumes continuously grows. Although the classical dose modulation Proximity Effect Correction is able to provide sufficient process control to the mainstream products, an increased number of published and wafer data show that the mask process is becoming a nonnegligible contributor to the 28nm technology yield. We will show in this paper that a novel approach of mask proximity effect correction is able to meet the dual challenge of the new generation of masks. Unlike the classical approach, the technique presented in this paper is based on a concurrent optimization of the dose and geometry of the fractured shots. Adding one more parameter allows providing the best possible compromise between accuracy and writing time since energy latitude can be taken into account as well. This solution is implemented in the Inscale software package from Aselta Nanographics. We have assessed the capability of this technology on several levels of a 28nm technology. On this set, the writing time has been reduced up to 25% without sacrificing the accuracy which at the same time has been improved significantly compared to the existing process. The experiments presented in the paper confirm that a versatile proximity effect correction strategy, combining dose and geometry modulation helps the users to tradeoff between resolution/accuracy and e-beam write time.

Advanced mask rule check (MRC) tool

As patterns on photomasks are getting more complex due to RET technologies, mask rule check (MRC) has become an essential process before manufacturing photomasks. Design rule check (DRC) tools in the EDA field can be applied for MRC. However, photomask data has unique characteristics different from IC design, which causes many problems when handling photomask data in the same way as the design data. In this paper, we introduce a novel MRC tool, SmartMRC, which has been developed by SII NanoTechnology in order to solve these problems and show the experimental results performed by DNP. We have achieved high performance of data processing by optimizing the software engine to make the best use of mask datas characteristics. The experimental results show that only a little difference has been seen in calculation time for reversed pattern data compared to non-reversed data. Furthermore, the MRC tool can deal with various types of photomask data and Jobdec in the same transparent way by reading them directly without any intermediate data conversion, which helps to reduce the overhead time. Lastly it has been proven that result OASIS files are several times smaller than GDS files.

Evaluation of OASIS.VSB (SEMI P44) for practical use

Over the last 5 years, Japanese consortium, Semiconductor Leading Edge Technologies Inc. (Selete), lead the way in developing unified mask data format. Specification of the format was released as OASIS.VSB and registered to SEMI standard, P44. It is expected that using OASIS.VSB would reduce TAT and improve efficient usage of data infrastructure. OASIS.VSB has advantages for mask data preparation since OASIS.VSB is based on OASISTM (SEMI P39) and OASIS compliant software is already commercially available. Although fundamental evaluation of OASIS.VSB have been made by Selete on technical feasibility with VSB mask writers, its performance and advantage of data handling improvement is still controversial. We have been evaluating OASIS.VSB in order to estimate the impact of data handling improvement at mask manufacturer. Figure 1 shows that OASIS.VSB has good compression ratio compared to certain VSB mask data format. Although compression ratio partly depends on data and conversion software, OASIS.VSB is about 0.7 times as small as VSB data format on weighted basis average. Furthermore, we have confirmed by simulation that OASIS.VSB can hardly affect shot count and writing time. Unification of mask data format by OASIS.VSB can realize flexible mask data preparation (MDP) and reduce a cost of data storage. To achieve further TAT reduction, it is necessary to apply OASIS.VSB to not only mask writing data but other mask making processes such as die to database inspection and mask rule check (MRC).

Evaluation of mask data preparation with OASIS and P10

OASIS (Open Artwork System Interchange Standard) is the new stream format to replace conventional GDSII and has become a SEMI standard 2003. Also, some EDA software tools already support OASIS. OASIS can apply not only layout design field but also photomask industory. OASIS is effective to reduce data volume even if it is a fractured data, therefore it is expected to solve file size explosion problem. From mask manufacturers perspective, it is also necessary to consider mask layout information. In present, there are various kinds of layout information and jobdeck formats. These circumstances require complicated data handling and preparation process at the mask manufacturers. Computerized automatic process needs to be more utilized to eradicate mistakes and miscommunications at the planning department. SEMI standard P10 (Specification of Data Structures for Photomask Orders) is one of the solutions. P10 is basically intended to communicate about mask order data which include layout information. This paper reports the result of evaluation of mask data preparation unified with two SEMI standards: P39 (OASIS) and P10. We have developed a reticle pattern viewer (HOTSCOPE) which can view photomask data with combined OASIS with P10. Figure 1 shows connection between mask data formats, which include OASIS and P10 format with our reticle pattern viewer. HOTSCOPE provides reviewing mask data as a photomask image. It will interface between device manufacturers and mask manufacturers.

Reticle SEM specifications required for lithography simulation

We investigated the specifications of scanning electron microscope required for the lithography simulation based on the edge data extracted from an actual reticle pattern in the assurance of reticle pattern in which two-dimensional optical proximity correction is applied. Impacts of field of view, positioning error and image distortion on a lithography simulation were studied experimentally. For the reticle pattern assurance in hp90, the field of view of larger than 16 μm squares, the positioning error within +/- 1 μm and the magnification error of less than 0.3% are needed. Under these conditions, wafer image can be predicted with sufficient accuracy by the simulation.

EB resolution capability with CP exposure

We are evaluating the resolution capability of character projection (CP) exposure method using a Multi Colum Cell Proof of Concept (MCC-POC) tool. Resolving of 14nm half pitch (HP) 1:1 line and space (LS) patterns are confirmed with fine openings of a DNP fabricated CP mask for 10:1 de-magnification ratio. CP exposure has been proven to exhibit high resolution capabilities even under the most challenging optimization conditions that are required for throughput enhancement. As a result of evaluating the resolution capability of CP technology, it became apparent that the CP technology has strong potentials to meet future challenges in two areas. One is where an increased number of CP with variable illumination technology gives a higher throughput which has been the main objective behind the development of this technology, and the other is to achieve higher resolution capability that is one of the strengths of CP exposure method. We also evaluated the resolution on Quartz mask blanks instead of Si wafers and obtained 18nm HP 1:1 resolution with CP exposure.

Verification of Mask Manufacturing Load Estimation (MiLE)

The design shrinking of semiconductor devices and the pattern complexity generated after OPC (optical proximity correction) have an impact on the two major cost consuming processes in mask manufacturing, EB (electron beam) writing and defect assurance. Mask-DFM (design for manufacturing) is a technique with various steps ranging from the design to the mask manufacturing to produce the mask friendly designs and to reduce the workload in the advanced mask production. We have previously reported on our system, called MiLE (Mask manufacturing Load Estimation), which quantifies the mask manufacturing workload by using the results of mask layout analyses. MiLE illustrates the benefits of mask-DFM efforts as numerical indexes and accelerates the DFM approaches. In this paper, we will show the accuracy of the workload estimation of the advanced devices by the comparison between the indexes and the process times in the actual mask manufacturing. The throughput of MiLE calculation of the production masks of a 65nm device was measured.

Making of P10-JOBDECK with OASIS and GDS-II fit for practical use

Recently, mask design has been becoming more complex with the increase of data volume. Therefore, it requires more functionality and portability in the mask specification and layout definition for the efficient data handling together with industry standard. SEMI-P10 order format has universal layout definition for the all sorts of mask specifications. We expect OASISTM (Open Artwork System Interchange Standard; SEMI standard P39) instead of conventional GDS-II to come into wide use as a more compressive stream format for 45nm node and beyond. The OASIS format is suitable for the enormous pattern file size and sub-nanometer design grid. Although SEMI-P10 is convenient to achieve all of our requirements, its complete definition is very complicated and is difficult to set up full parameters in the primary stage of mask design for production chips. In this work, we focused on minimum syntax of the chip location information from portion of SEMI-P10. And we define P10-JOBDECK as a subset of whole SEMI-P10 regulations. So, by use of P10-JOBDECK and OASIS data format, we have built up the new data handling infrastructure such as data file transfer and pattern layout viewing for the high-end mask manufacturing. In this system, the coordinates of P10-JOBDECK are described in 4X image with mirror inversion and tone reversal parameters. We use 1X coordinates in P10-JOBDECK for the pattern data files because they are the dimensions familiar to the designer, and the transformation for the mask shop is handled automatically. This style is effective for shortening the data conversion time and preventing mishandling of data. We also developed the additional viewer functions of HOTSCOPE® to confirm the pattern layout on the digital display. It is possible to add mask DFM information (design information for mask manufacturability) by the extension to the full SEMI-P10 syntax and by the use of built-in OASIS properties in the future. In this paper, we will discuss the practical application of P10-JOBDECK and the performance results of HOTSCOPE.