Shoji Kubono

A 256 Mb multilevel flash memory with 2 MB/s program rate for mass storage applications

A 256 Mb flash memory in 0.26 /spl mu/m CMOS on a 138.6 mm/sup 2/ die uses a multilevel technique. The AND-type memory cell suitable for multilevel operation is used. One sector consists of(8192+256) memory cells. As two bits of data are stored in one physical cell, logical sector size is (16384+512)b. Sector erase and program times are both 1 ms/sector (2048+64B), so typical programming rate is 2 MB/s. By increasing sector size to four times that in conventional two-level flash memories, program throughput is kept acceptable for mass-storage applications, even with multi-level operation.

A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current

A 4-Mb pseudo static RAM (PSRAM) suitable for universal battery usage is described. The wide voltage range, 2.6+or-1 V, is set to target the power supply voltage of the PSRAM considering various voltage levels and charging-discharging characteristics of batteries. A double-to-single automatically switchable booster is developed to provide the wide voltage range operation. To reduce the power dissipation of data retention for battery usage a low-power back-bias generator with a new substrate-level sensor and a temperature-dependent self-refresh timer with a unique internal refresh control scheme are demonstrated. A PSRAM operation ranging from 1 V to more than 5 V was obtained and a 3- mu A data retention current was realized at room temperature in contrast with 7 mu A at 70 degrees C and V/sub cc/ of 2.6 V. This PSRAM allows a 20-Mbyte RAM disk to retain data for two months with a single lithium battery. >

A 126.6 mm/sup 2/ AND-type 512 Mb flash memory with 1.8 V power supply

A 512 Mb AND-type flash memory in 0.18 /spl mu/m CMOS achieves 126.6 mm/sup 2/ die size, uses a multilevel technique, and adapts to 1.8 V operation. In addition, a read-modify-write mode enables programming free from pre-programmed states.