Atsushi Nozoe
Hitachi
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Publication
Featured researches published by Atsushi Nozoe.
international solid-state circuits conference | 1999
Atsushi Nozoe; Hiroaki Kotani; T. Tsujikawa; K. Yoshida; Kazunori Furusawa; Masataka Kato; T. Nishimoto; Hitoshi Kume; H. Kurata; N. Miyamoio; Shoji Kubono; I. Kanamitsu; K. Koda; Takeshi Nakayama; Y. Kouro; A. Hosogane; Natsuo Ajika; Kazuo Kobayashi
A 256 Mb flash memory in 0.26 /spl mu/m CMOS on a 138.6 mm/sup 2/ die uses a multilevel technique. The AND-type memory cell suitable for multilevel operation is used. One sector consists of(8192+256) memory cells. As two bits of data are stored in one physical cell, logical sector size is (16384+512)b. Sector erase and program times are both 1 ms/sector (2048+64B), so typical programming rate is 2 MB/s. By increasing sector size to four times that in conventional two-level flash memories, program throughput is kept acceptable for mass-storage applications, even with multi-level operation.
international solid-state circuits conference | 1995
Atsushi Nozoe; T. Yamazaki; H. Sato; Hiroaki Kotani; S. Kubono; K. Manita; T. Tanaka; Takayuki Kawahara; Masataka Kato; Katsutaka Kimura; Hitoshi Kume; R. Hori; T. Nishimoto; S. Shukuri; A. Ohba; Y. Kouro; O. Sakamoto; A. Fukumoto; M. Nakajima
A 3.3 V single-supply 32 Mb flash memory realizing a 512B per sector program/erase unit features serial sector read, sector program and sector erase modes. By using AND cells and connecting one sense and latch (SL) circuit to every data line (DL) pair, these modes can handle data strictly sector by sector (512B). The same sector size for both programming and erasing simplifies the rewrite operation to a small number of sectors and prevents system performance degradation. The chip is implemented in a 0.45 /spl mu/m triple-well CMOS process.
international solid-state circuits conference | 2001
Tatsuya Ishii; Kazuyoshi Oshima; Hiroshi Sato; Satoshi Noda; Jiro Kishimoto; Hiroaki Kotani; Atsushi Nozoe; Kazunori Furusawa; Takayuki Yoshitake; Masataka Kato; Masahito Takahashi; Akihiko Sato; Shoji Kubono; Kiichi Manita; Kenji Koda; Takeshi Nakayama; Akira Hosogane
A 512 Mb AND-type flash memory in 0.18 /spl mu/m CMOS achieves 126.6 mm/sup 2/ die size, uses a multilevel technique, and adapts to 1.8 V operation. In addition, a read-modify-write mode enables programming free from pre-programmed states.
IEEE Journal of Solid-state Circuits | 1991
Masashi Horiguchi; M. Aoki; Jun Etoh; Kiyoo Itoh; Kazuhiko Kajigaya; Atsushi Nozoe; Tetsurou Matsumoto
The authors present a dynamic RAM (DRAM) voltage limiter with a burn-in test mode. It features a dual-regulator dual-trimmer scheme that provides a precise stress voltage in a burn-in test while maintaining a constant limited voltage under normal operation. A regulator is used to preserve a constant difference between the internal burn-in voltage and the supply voltage. Two sets of trimmers reduce the voltage deviations of both the burn-in and normal-operation voltages within +or-0.13 V. The circuits are implemented in a 16-Mb CMOS DRAM. A burn-in voltage regulated to +or-50 mV at an ambient temperature up to 120 degrees C is obtained simply by elevating the supply voltage to 8 V as in conventional burn-in procedures. >
Archive | 2002
Takashi Horii; Keiichi Yoshida; Atsushi Nozoe
Archive | 1997
Takayuki Kawahara; Hiroshi Sato; Atsushi Nozoe; Keiichi Yoshida; Satoshi Noda; Shoji Kubono; Hiroaki Kotani; Katsutaka Kimura
Archive | 2002
Michitaro Kanamitsu; Tetsuya Tsujikawa; Toshinori Harada; Hiroaki Kotani; Shoji Kubono; Atsushi Nozoe; Takayuki Yoshitake
Archive | 2004
Tetsuya Tsujikawa; Atsushi Nozoe; Michitaro Kanamitsu; Shoji Kubono; Eiji Yamamoto; Ken Matsubara
Archive | 1994
Toshio Sasaki; Toshihiro Tanaka; Atsushi Nozoe; Hitoshi Kume
Archive | 2000
Yoshinori Sakamoto; Tatsuya Ishii; Atsushi Nozoe; Hitoshi Miwa; Kazuyoshi Oshima
