Shoji Otaka

A low-power low-noise accurate linear-in-dB variable gain amplifier with 500 MHz bandwidth

A linear-in-dB variable-gain amplifier (VGA) using a pre-distortion circuit to generate the gain-control signal is fabricated in a BiCMOS process with f/sub T/=20 GHz. The VGA comprises two cascaded stages of signal-summing VGA and has a variable-gain range of over 70 dB. It can operate at up to 500 MHz and dissipates 36 mW from a 3-V supply. A noise figure of below 5 dB and IIP3 of over -38 dBm at 43-dB gain were obtained. The VGA achieved a gain error of less than 2 dB over 70-dB gain range, and it occupies approximately 1 mm/sup 2/. The VGA is applicable to future code division multiple access (CDMA) receivers.

A 7-GHz 1.8-dB NF CMOS low-noise amplifier

A 7-GHz low noise amplifier (LNA) was designed and fabricated using 0.25µm-CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads are adopted to improve the gain and the noise performances. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. The associated gain of 8.9dB, minimum noise figure of 1.8dB and input-referred 3rd-order intercept point of +8.4dBm were obtained at 7GHz. The LNA consumes 6.9mA from a 2.0V supply voltage. These measured results indicate the feasibility of a CMOS LNA with the appropriate techniques for low-noise and high-linearity applications over 5GHz.

A 950 MHz rectifier circuit for sensor networks with 10 m-distance

A high-sensitivity rectifier is fabricated in a 0.3 /spl mu/m CMOS technology. The circuit can rectify an RF signal less than the NMOS threshold voltage by using a bias voltage between the gate and the drain terminals of a transistor. The IC achieves a 950 MHz signal rectification over -14 dBm corresponding to 10 m-distance communication and recharges a 1.2 V secondary battery.

High-speed CMOS I/O buffer circuits

Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. An all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates is described. The circuits are also compatible with voltage-mode signal levels for ECL input and MOS output circuits. >

A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications

Low-cost CMOS PAs for mobile terminals have been a focus of attention in recent years. Self-contained, linear CMOS PAs are particularly attractive for smooth replacement of conventional compound semiconductor PA products. The main challenge concerning the linear CMOS PAs is to improve their power efficiency. Doherty PAs improve the average power efficiency by means of backoff efficiency boosting; however, their applicable carrier frequency range is narrow owing to the high-order output network. Supply modulation is another technique to improve the PA back-off efficiency. Although hybrid modulators have been studied for CMOS polar transmitters [1,2], none of them have satisfied full specs of modulation bandwidth and the output power for 4G cellular applications. The area overhead is also unacceptable for application to a self-contained linear PA. A class-G supply modulator relaxes the limitations by receiving external, discrete levels of supply voltages [3]. However, it still requires a costly extra DC-DC converter for multilevel supply voltages.

A 1.5GHz-modulation-range 10ms-modulation-period 180kHz rms -frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application

A frequency modulated continuous-wave (FMCW) radar using triangular modulation is one of the promising candidates for realizing a CMOS radar IC [1–3]. Range and velocity resolutions of the FMCW radar are determined by the bandwidth and period of triangular modulation [4]. A short-range measurement requires wide (several GHz) bandwidth, while a long-range measurement with high-velocity resolution requires moderate (hundreds of MHz) bandwidth and long (several ms) period. Furthermore, since frequency error in the FMCW signal deteriorates range and velocity accuracy, a highly linear frequency chirp signal is required. However FMCW radars reported so far [2,3] exhibit a period up to 1.5ms because a long period degrades the chirp linearity in a conventional analog PLL. In this work, an analog/digital mixed-mode 82GHz FMCW synthesizer with 1.5GHz bandwidth, a period from 1ms to 10ms and less than 180kHzrms frequency error is described. The achieved performance corresponds to range and velocity resolutions of 10cm and 1.4km/h, respectively.

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

A series combining transformer(SCT)-based, watt-level 1.9 GHz linear CMOS power amplifier with an on-chip linearizer is demonstrated. Proposed compact, predistortion-based linearizer is embedded in the two-stage PA to compensate AM-PM distortion of the cascode power stages, and improve ACLR of 3GPP WCDMA uplink signal by 2.6 dB at 28.0 dBm output power. The designed interstage power distributor with one tuning inductor contributes to low-loss power supply for the driver stage and high common-mode stability of the whole PA. Moreover, a newly developed PVT variation- tolerant cascode biasing circuit guarantees highly accurate bias voltages in a wide supply voltage range from 2.5 V to 3.6 V. The test chip demonstrates maximum output power of 28.3 dBm at 1.95 GHz, satisfying 3GPP WCDMA spectrum mask with die area of 5.4 mm2.

A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment

A 1.9 GHz quadrature modulator with an onchip 90/spl deg/ phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm/spl times/2.14 mm.

A voltage ratio-based efficiency control method for 3 kW wireless power transmission

This paper presents a novel control method for wireless power transmission (WPT). The proposed method can maximize the power efficiency only by controlling the voltage ratio between the primary and the secondary side. Experimental measurement results of the prototype system with 3 kW power transmission show the efficiency difference between the proposed control method and the available maximum value is less than 0.3 % even with a large variation of coil-to-coil distance and load voltage. The automatic controller for the proposed method provides the load-following operation, maintaining both constant power and high efficiency, using a WLAN connection.

RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip

Recently, direct tunneling gate oxide MOSFETs have shown the potential of enabling extremely high RF performance in analog applications. An excellent cutoff frequency of more than 150 GHz was reported at a gate length of less than 0.1 /spl mu/m. In this paper, RF noise characteristics of the MOSFETs are reported in detail. The gate oxide thickness and supply voltage dependencies were investigated. In addition, NMOS LNA (low noise amplifier) circuits made with 1.5 nm gate oxide MOSFETs were evaluated for the first time. Good RF analog circuit operation with very low noise and high gain was confirmed.