Kohei Onizuka

A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications

Low-cost CMOS PAs for mobile terminals have been a focus of attention in recent years. Self-contained, linear CMOS PAs are particularly attractive for smooth replacement of conventional compound semiconductor PA products. The main challenge concerning the linear CMOS PAs is to improve their power efficiency. Doherty PAs improve the average power efficiency by means of backoff efficiency boosting; however, their applicable carrier frequency range is narrow owing to the high-order output network. Supply modulation is another technique to improve the PA back-off efficiency. Although hybrid modulators have been studied for CMOS polar transmitters [1,2], none of them have satisfied full specs of modulation bandwidth and the output power for 4G cellular applications. The area overhead is also unacceptable for application to a self-contained linear PA. A class-G supply modulator relaxes the limitations by receiving external, discrete levels of supply voltages [3]. However, it still requires a costly extra DC-DC converter for multilevel supply voltages.

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

A series combining transformer(SCT)-based, watt-level 1.9 GHz linear CMOS power amplifier with an on-chip linearizer is demonstrated. Proposed compact, predistortion-based linearizer is embedded in the two-stage PA to compensate AM-PM distortion of the cascode power stages, and improve ACLR of 3GPP WCDMA uplink signal by 2.6 dB at 28.0 dBm output power. The designed interstage power distributor with one tuning inductor contributes to low-loss power supply for the driver stage and high common-mode stability of the whole PA. Moreover, a newly developed PVT variation- tolerant cascode biasing circuit guarantees highly accurate bias voltages in a wide supply voltage range from 2.5 V to 3.6 V. The test chip demonstrates maximum output power of 28.3 dBm at 1.95 GHz, satisfying 3GPP WCDMA spectrum mask with die area of 5.4 mm2.

A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique

A watt-level, fully integrated 1:1 Doherty power amplifier for 2.4 GHz band is demonstrated in 65 nm CMOS. Both high peak output power of +30.5 dBm and high PAE of 23% at 6 dB power back-off are achieved by the proposed compact output network. A newly introduced reliability enhancement technique for sub-PA prolongs time to failure by up to 75% as well. The PA satisfies IEEE 802.11b and 11g spectrum masks at output power levels of 25.5 and 21.5 dBm respectively, from supply voltage of 3.3 V.

A 2.4 GHz CMOS Doherty power amplifier with dynamic biasing scheme

A watt-level, fully integrated 1:1 Doherty power amplifier with dynamic biasing scheme is demonstrated in 65 nm CMOS. The newly implemented dynamic biasing scheme for sub-PA solves the gain-linearity trade-off of the Doherty PA with enough back-off efficiency improvement, and protects the gate oxide of the sub-PA from over-voltage stress as well. The PA delivers 30.4 dBm of peak output power with maximum 6 points of PAE improvement compared with a class-B PA, and satisfies IEEE 802.11b and 11g spectrum masks at output power levels of 24.3 and 23.2 dBm, respectively, from supply voltage of 3.3 V.

The Wireless Workhorse: Mixed-Signal Power Amplifiers Leverage Digital and Analog Techniques to Enhance Large-Signal RF Operations

The ever-growing demand for higher data rates, power efficiency, and robust operations poses increasingly stringent performance requirements on wireless transceiver systems. This is particularly critical for mobile devices in both commercial and defense applications, where improving system size, weight, and power metrics and extending the battery lifetime are often the primary concerns. The power amplifier (PA) serves as the interface between the RF transmitter system and the antenna and is often considered one of the most critical building blocks in a wireless transceiver. This is because the PAs performance has critical impacts on multiple major transmitter metrics, including the output power level, power efficiency, bandwidth, and signal fidelity, and therefore governs the overall quality of service (QoS) of the wireless link [1], [2]. Moreover, due to their large-signal and high-power operations at RF frequencies, PAs often encounter unique design challenges and tradeoffs that deserve special attention [3].

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations

The RF power amplifier (PA) is typically the most power hungry and area consuming block in a wireless transceiver system. A viable RF PA solution should offer competitive power and area efficiency while maintaining high-performance large-signal RF operations. Fully integrated RF PA in CMOS has been an area of active research and development over the past years. Recently, there has been a surge of interest to leverage the mixed-mode, analog and digital, computational and signal processing capability in CMOS to radically enhance RF CMOS PA solutions and offer unique functionalities in parallel. This paper reviews several recently reported circuit design techniques of CMOS PAs. All of these techniques take advantage of computation and integration advantages of CMOS process and can potentially lead to competitive PA solutions compared to traditional III-V HBT PA solutions.

Session 2 overview: Power amplifiers

Improving efficiency at back-off power levels has become an active area of research to support spectrally efficient modulation schemes with high peak-to-average power ratios. Doherty power-amplifier topology and envelope-tracking supply modulation are key enablers to improve the back-off efficiency of transmitters. Increasing signal bandwidths for applications such as carrier-aggregation LTE and WiFi 802.11ac poses challenges for supply modulation. Implementing the Doherty topology for 5G applications operating at mm-wave frequencies is an active area of research.

F2: High-performance frequency generation for wireless and wireline systems

Frequency generation equips nearly all electronic systems and is a critical performance factor for many of them. This forum focuses on wireless and wireline systems, which demand high performance clocks, and looks for synergies between them. The topics cover both fundamental techniques and specific applications. State-of-the-art techniques will be explored in depth, such as high-FOM VCOs, digital-to-time converters, sampling phase-detectors, synthesizable and digital PLLs. Attention will also be on booming applications, such as high-speed wireline, FMCW radar, mm-wave and THz. The forum aims at bringing together the contemporary top interests with added value and sowing seeds to inspire the future.

Head ballistocardiogram based on wireless multi-location sensors.

Recently a wearable BCG monitoring technique based on an accelerometer worn at the ear was demonstrated to replace a conventional bulky BCG acquisition system. In this work, a multi-location wireless vital signs monitor was developed, and at least two common acceleration vectors correlating to sitting-BCG were found in the supine position by using head PPG signal as a reference for eight healthy human subjects. The head side amplitude in the supine position is roughly proportional to the sitting amplitude that is in turn proportional to the stroke volume. Signal processing techniques to identify J-waves in a subject having small amplitude was also developed based on the two common vectors at the head side and top.

A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller

A transformer-based dual band watt-level linear CMOS power amplifier is demonstrated for upcoming SDR mobile terminals. The proposed AM-PM distortion canceller improves ACLR of 3GPP WCDMA uplink signal by 2.6dB at 28.0dBm output power, and the designed interstage power distributor contributes to low-loss power supply for the driver stage and high common-mode stability. Moreover, a newly developed cascode biasing circuit guarantees AM-AM linearity of the PA in a wide supply voltage range from 2.5V to 3.6V. The test chip demonstrates peak output powers of 28.3dBm at 1.95GHz and 23.7dBm at 2.4GHz satisfying 3GPP WCDMA and IEEE802.11g spectrum masks with die area of 5.4mm2.