Shunichi Kikuchi

MCM and bare chip technology for a wide range of computers

For a versatile MCM packaging technology with bare chip interconnection, an adequate patterned substrate and efficient cooling have been developed. A lineup of MCMs from a high-end supercomputer to a low-end portable PC are arranged by the combination of flip-chip and substrate technologies. More than thirty kinds of MCMs have been developed and are in production. These MCMs are classified into MCM-D and MCM-L, which are applied to both bare flip-chip devices of area bump and peripheral bump type. This effective combination of MCM technology for a wide range computers is discussed in this paper.

High performance MCM-D technology

FUJITSU has developed an MCM-D technology which uses bare chips on composite thin films for mounting CMOS chips with high density and low cost. The first use of this technology is for the K6000 Series business server. This MCM technology can be applied to a wide range of computers, from workstations to mainframes to reduce costs and improve performance. This paper focuses on the MCM packaging technology, MCM substrate technology, cooling technology and numerical analysis technique.<<ETX>>

Thermal modeling and experimental study of 3D stack package with hot spot consideration

This paper provides a unique approach to thermal modeling of BEOL (Back End Of Line) layers in a 3D stacked LSI and introduces a novel cold plate design method by using a 30 mm by 30 mm LSI as an example. The paper focuses on BEOL thermal characterization, flow rate control in branch-channels and the micro-channels behind them in a cold plate in accordance with a power map of the LSI, and an experimental setup for thermal verification. The power map had several considerable hot spots. The cold plate was able to considerably reduce temperature differences by 5°C all across the top surface of the LSI on the load condition of 120 W/cm2 for hot spots and 60.5 W/cm2 for other areas with regard to heat density, at a flow rate of 1 L/min. to the cold plate inlet. It also achieved a low of 5 kPa in pressure loss while the flow rate ratio of hot spots to others was controlled to approximately 5:1.

Thermal characterization and modeling of BEOL for 3D integration

Thermal design of 3D integration is one of most important issues for implementing this technology in applications. The lack of uniformity in micro-bump interconnection and high thermal resistance in BEOL (Back End of Line) in chips may limit the heat dissipation path for the cooling method. Firstly, in this study, through steady state measurement and FEM analysis of a F2F (Face to face) sample, which was made of an actual LSI, the thermal resistance of BEOL was derived and a 3D stacked FEM model in chip size was built for thermal design use. Secondly, the cooling performance of the thermal bumps for hotspots was compared with varying bump pitches in both the FEM analysis and measurement. Thermal bumps can lower the temperature of not only the area where they are placed but also areas surrounded by them. Moreover, it can be thought that partially dense thermal bumps for hotspots are not superior to uniformly dense ones in terms of controlling the maximum temperature in a chip. However, they provide almost the same performance in terms of decreasing the temperature differences in the chip.

An experimental setup of stacked thermal chips with selectable cell heaters for 3D integration design

This paper introduces a unique experimental setup of stacked thermal chips consisting of 100 polysilicon heaters in a 30 mm by 30 mm area. Temperature distributions in the stacked chips were measured and characterized with varying power in the heaters at a range exceeding 300 W in total; then thermal simulation models were built for 3D integration design.

Thermal fatigue life evaluation of CSP joints by mechanical fatigue testing

The interrelation between a thermal cycle test and a mechanical shear fatigue test has been studied for CSP joints from the view point of fatigue life and the microstructural damage of solder joints. The fatigue lives in both methods are almost equivalent even though loading method is different. From the viewpoint of microstructure, the fact is attributed to that the transgranular failure is predominant mode and a microstructural coarsening which is induced by thermal loading and stress equivalent for both the thermal cycle test and the mechanical shear fatigue test.

Low-cycle fatigue testing and thermal fatigue life prediction of electroplated copper thin film for through hole via

Abstract A new fatigue test method was proposed for low-cycle fatigue lives of electroplated copper thin films for the through hole (TH) in a printed wiring board. And the low-cycle fatigue lives were investigated according to the proposed method. Furthermore, thermal stress analysis of the TH with the finite element method was performed to predict thermal fatigue life of the TH based on Manson-Coffin law for electroplated copper thin films obtained from the low-cycle fatigue test. Low-cycle fatigue damage in the electroplated copper thin film was occurring in the grain boundaries and the damage mechanism was found same as that for thermal fatigue damage in TH in the printed wiring board. And the fatigue life of TH predicted from the Manson-Coffin law at the maximum temperature of thermal fatigue test was good agreement with the thermal fatigue life obtained from the experimental result of thermal fatigue test.

Study on low-cycle fatigue testing and therrmal fatigue life prediction of electroplated copper thin film for through hole via

A new fatigue test method was proposed for low-cycle fatigue lives of electroplated copper for the through hole via (THV) in a printed wiring board. And the fatigue life of THV predicted from the Manson-Coffins law of thermal fatigue test was good agreement with the thermal fatigue life obtained from the experimental result of thermal fatigue test of THV.