Naoaki Nakamura

Thermal modeling and experimental study of 3D stack package with hot spot consideration

This paper provides a unique approach to thermal modeling of BEOL (Back End Of Line) layers in a 3D stacked LSI and introduces a novel cold plate design method by using a 30 mm by 30 mm LSI as an example. The paper focuses on BEOL thermal characterization, flow rate control in branch-channels and the micro-channels behind them in a cold plate in accordance with a power map of the LSI, and an experimental setup for thermal verification. The power map had several considerable hot spots. The cold plate was able to considerably reduce temperature differences by 5°C all across the top surface of the LSI on the load condition of 120 W/cm2 for hot spots and 60.5 W/cm2 for other areas with regard to heat density, at a flow rate of 1 L/min. to the cold plate inlet. It also achieved a low of 5 kPa in pressure loss while the flow rate ratio of hot spots to others was controlled to approximately 5:1.

Thermal characterization and modeling of BEOL for 3D integration

Thermal design of 3D integration is one of most important issues for implementing this technology in applications. The lack of uniformity in micro-bump interconnection and high thermal resistance in BEOL (Back End of Line) in chips may limit the heat dissipation path for the cooling method. Firstly, in this study, through steady state measurement and FEM analysis of a F2F (Face to face) sample, which was made of an actual LSI, the thermal resistance of BEOL was derived and a 3D stacked FEM model in chip size was built for thermal design use. Secondly, the cooling performance of the thermal bumps for hotspots was compared with varying bump pitches in both the FEM analysis and measurement. Thermal bumps can lower the temperature of not only the area where they are placed but also areas surrounded by them. Moreover, it can be thought that partially dense thermal bumps for hotspots are not superior to uniformly dense ones in terms of controlling the maximum temperature in a chip. However, they provide almost the same performance in terms of decreasing the temperature differences in the chip.

An experimental setup of stacked thermal chips with selectable cell heaters for 3D integration design

This paper introduces a unique experimental setup of stacked thermal chips consisting of 100 polysilicon heaters in a 30 mm by 30 mm area. Temperature distributions in the stacked chips were measured and characterized with varying power in the heaters at a range exceeding 300 W in total; then thermal simulation models were built for 3D integration design.

Development of a stacking technology for large-sized chips using non-conductive film

A chip stacking process technology using high mass productivity non-conductive film (NCF) has been developed, with assumptions for the central processing unit (CPU) in high-end servers. With this process, a 23 mm by 23 mm chip with a bump pitch of 40 μm was successfully stacked onto another, and 296,000 bumps were jointed in total. In the development of the chip stacking process, in order to measure NCF behavior in the thermo compression flip chip (TCFC) bonding process, the head position detecting mechanism of a flip chip bonder (FCB) measured NCF deformation between the chip and a bare silicon plate in real time. During the measurement, the bonding head applied a constant load to the NCF, and its temperature went up. In order to observe the effect of chip size, NCF deformation was measured at three chip sizes. The amount of deformation of a large-sized chip was found to be less than that of a small-sized chip under the same pressure applied to the chips. This result revealed a limitation of the chip stacking process for large-sized chips using NCF. In addition, variations in bump height or silicon thickness occurring in the LSI manufacturing process were found to cause various problems in the chip stacking process using NCF. These problems were solved using a special bonding tool. Moreover, to suppress voids, the behavior of voids was observed, which found voids remaining in the chip corners. Shaping NCF in the X-shape suppressed these corner voids.