Shusaku Yamaguchi
Fujitsu
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Publication
Featured researches published by Shusaku Yamaguchi.
international solid-state circuits conference | 1997
Atsushi Hatakeyama; Hirohiko Mochizuki; Tadao Aikawa; Masato Takita; Yuki Ishii; Hironobu Tsuboi; Shinya Fujioka; Shusaku Yamaguchi; Makoto Koga; Yuji Serizawa; Koichi Nishimura; Kuninori Kawabata; Yoshinori Okajima; Michiari Kawano; Hideyuki Kojima; Kazuhiro Mizutani; Toru Anezaki; Masatomo Hasegawa; Masao Taguchi
This 256 Mb synchronous DRAM with 1 ns clock access is stable against temperature, voltage, and process variation by use of an innovative register-controlled delay locked loop (RDLL). Unlike most conventional high-density DRAMs, the bit-lines are placed above the storage capacitors in this DRAM to relax design rules of the core area. The noise issues are analyzed and resolved to help implement the technology in mass production of 0.28 to 0.24 /spl mu/m 200 MHz DRAMs.
Archive | 1998
Shusaku Yamaguchi
Archive | 2000
Shusaku Yamaguchi
Archive | 1998
Koichi Nishimura; Shusaku Yamaguchi
Archive | 2008
Shusaku Yamaguchi
Archive | 1997
Shusaku Yamaguchi; Atsushi Hatakeyama; Masato Takita; Tadao Aikawa; Hirohiko Mochizuki
Archive | 1989
Atsushi Hatakeyama; Shusaku Yamaguchi
Archive | 2008
Shusaku Yamaguchi
Archive | 1997
Tadao Aikawa; Hirohiko Mochizuki; Atsushi Hatakeyama; Shusaku Yamaguchi; Koichi Nishimura
Archive | 2008
Shusaku Yamaguchi
