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Shyh-Horng Lin

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Publication

Featured researches published by Shyh-Horng Lin.

international test conference | 2005

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction

Laung-Terng Wang; Khader S. Abdel-Hafez; Xiaoqing Wen; Boryau Sheu; Shianling Wu; Shyh-Horng Lin; Ming-Tung Chang

This paper describes time-division demultiplexing and multiplexing of high-data-rate scan patterns applied on I/Os into low-data-rate scan patterns applied on VirtualScan compression circuitry to further reduce test application time and test pin-count without coverage loss

Archive | 2002

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Laung-Terng Wang; Ming-Tung Chang; Shyh-Horng Lin; Hao-Jan Chao; Jaehee Lee; Hsin-Po Wang; Xiaoqing Wen; Po-Ching Hsu; Shih-Chia Kao; Meng-Chyi Lin; Sen-Wei Tsai; Chi-Chan Hsu

Archive | 2003

Method and apparatus for unifying self-test with scan-test during prototype debug and production test

Laung-Terng Wang; Xiaoqing Wen; Khader S. Abdel-Hafez; Shyh-Horng Lin; Hsin-Po Wang; Ming-Tung Chang; Po-Ching Hsu; Shih-Chia Kao; Meng-Chyi Lin; Chi-Chan Hsu

Archive | 2003

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Laung-Terng Wang; Hsin-Po Wang; Xiaoqing Wen; Meng-Chyi Lin; Shyh-Horng Lin; Ta-Chia Yeh; Sen-Wei Tsai; Khader S. Abdel-Hafez

Archive | 2002

Method and system to optimize test cost and disable defects for scan and BIST memories

Laung-Terng Wang; Shyh-Horng Lin; Chi-Chan Hsu; Xiaoqing Wen; Anthony M. Vu; Yo Han Park; Hsin-Po Wang

Archive | 2004

Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

Laung-Terng Wang; Khader S. Abdel-Hafez; Xiaoqing Wen; Boryau Sheu; Fei-Sheng Hsu; Augusli Kifli; Shyh-Horng Lin; Shianling Wu; Shun-Miin Sam Wang; Ming-Tung Chang

Archive | 2005

IEEE Std. 1149.4 compatible analog BIST methodology

Chauchin Su; Shyh-Horng Lin; Laung-Terng L-T Wang

Archive | 2002

Procede et appareil permettant de diagnostiquer des pannes dans un circuit integre a l'aide de techniques de depannage integrees

Laung-Terny Wang; Ming-Tung Chang; Shyh-Horng Lin; Hao-Jan Chao; Jachee Lee; Hsin-Po Wang; Xiaoqing Wen; Po-Ching Hsu; Shih-Chia Kao; Meng-Chyi Lin; Sen-Wei Tsai; Chi-Chan Hsu

Archive | 2002

Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher Method and system for optimizing the test cost and deactivation defective for scan- and are mem

Laung-Terng Wang; Shyh-Horng Lin; Hsin-Po Wang; Xiaoqing Wen; Chi-Chan Hsu; Anthony M. Vu; Yo Han Park

Archive | 2002

Systeme de conception assiste par ordinateur pour automatiser la synthese de balayage au niveau du transfert de registre

Laung-Terng Wang; Shih-Chia Kao; Shyh-Horng Lin; Hsin-Po Wang; Xiaoqing Wen; Augusli Kilfi; Fei-Sheng Hsu

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Collaboration

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Xiaoqing Wen

NEC

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Laung-Terng Wang

Stanford University

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Hao-Jan Chao

National Taiwan University

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Khader S. Abdel-Hafez

Synopsys

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Shianling Wu

Kyushu Institute of Technology

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