Simon Jang

A physical model for hole direct tunneling current in p/sup +/ poly-gate pMOSFETs with ultrathin gate oxides

A model of the hole direct tunneling gate current accounting for heavy and light holes subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO/sub 2/-Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass m/sub oxh/=0.51 M/sub o/ for the parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p/sup +/ poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lower barrier heights, and are prevailing over the first subbands for reducing the oxide field down below 1 MV/cm.

Edge hole direct tunneling in off-state ultrathin gate oxide p-channel MOSFETs

This paper examines the edge direct tunneling (EDT) of hole from p+ polysilicon to underlying p-type drain extension in off-state p-channel MOSFETs having ultrathin gate oxide thicknesses (1.2-2.2 nm). It is found that for thinner oxide thicknesses, hole EDT is more pronounced over the conventional GIDL and gate-to-channel tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model accounting for heavy and light holes subbands in the quantized accumulation polysilicon surface is built explicitly. This model consistently reproduces EDT I-V and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.

Electrical Characterization and Materials Stability Analysis of

In this letter, a high-k composite oxide composed of La₂O₃ and HfO₂ is investigated for n-In_0.53Ga_0.47As metal-oxide-semiconductor (MOS) capacitor application. The composite oxide was formed by depositing five layers of La₂O₃(0.8 nm)/HfO₂(0.8 nm) on InGaAs with post deposition annealing at 500°C. The MOS capacitors fabricated show good inversion behavior, high capacitance, low leakage current, with excellent interface trap density (D_it) of 7.0×10¹¹ cm^-2eV^-1, small hysteresis of 200 mV and low capacitance equivalent thickness of 2.2 nm at 1 kHz were also achieved.

{\rm La}_{2}{\rm O}_{3}/{\rm HfO}_{2}

A novel technique to create a suspending stacked gate oxide and subsequently to fill in an embedded SiGe channel (ESC) between the gate oxide and the underlying silicon substrate is proposed for the first time to fabricate 28 nm p-metal–oxide–semiconductor field-effect transistors (p-MOSFET). Without Si surface passivation on the ESC, such an ESC structure could achieve a p-FET transconductance (Gm) gain of 26% higher and a better Ion–Ioff performance gain of 8% than that of conventional strained Si p-FETs with the source/drain (S/D) SiGe. Better S/D resistance (Rsd) in the resistance versus gate length plot and improved swing slope of the Id–Vgs plot indicates higher mobility in the ESC devices. Moreover, the off-state gate current of the ESC structure is also comparable to the conventional ones. From the x-ray photoelectron spectrum analysis, only the Si–O bonding, and no Ge–O bonding at the SiGe/SiO2 interface could account for this superior gate oxide integrity for the ESC and strained Si structure. Therefore, such a novel technique with an ESC structure is very promising for the 28 nm p-MOSFET devices era.

Composite Oxides on n-

The characteristics of Al2O3/InSb MOSCAPs processed with different postdeposition annealing (PDA) temperatures are investigated. X-ray photoelectron spectroscopy analysis shows a significant reduction of InSb-oxides after HCl plus trimethyl aluminum treatment and oxide deposition. Multifrequency capacitance-voltage (C-V) characteristics exhibit low-frequency and asymmetrical C-V behaviors, in which capacitance in the InSb conduction band side is lower than in the valence band side. The electrical properties of the MOSCAPs are sensitive to PDA temperature and degraded significantly at PDA temperature >300 °C. This degradation is closely related to the diffusion of In, Sb into Al2O3 as indicated by transmission electron microscopy analyses.

{\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}

The characteristics of Al2O3/InSb MOSCAPs processed with different postdeposition annealing (PDA) temperatures are investigated. X-ray photoelectron spectroscopy analysis shows a significant reduction of InSb-oxides after HCl plus trimethyl aluminum treatment and oxide deposition. Multifrequency capacitance-voltage (C-V) characteristics exhibit low-frequency and asymmetrical C-V behaviors, in which capacitance in the InSb conduction band side is lower than in the valence band side. The electrical properties of the MOSCAPs are sensitive to PDA temperature and degraded significantly at PDA temperature >300 °C. This degradation is closely related to the diffusion of In, Sb into Al2O3 as indicated by transmission electron microscopy analyses.

MOS Capacitors With Different Annealing Temperatures

Strained-Si technology is the Holy Grail for present semiconductor industry and is used extensively to boost the device performance, recently. However, the limitation of strained-Si technology has greatly perplexed us and need to investigate in detail. In this work, the low temperature ballistic measurement enables us to discriminate the origin of mobility enhancement under stress from the reduction of effective mass and/or the influence of different scattering mechanisms. It is found that the electron mobility enhancement under stress will become less sensitive when the gate length of device reaches ∼100 nm. The real mechanism of this phenomenon have be proved to the characteristic of device ballistic transport and the optimal stress design developed in this work can further extend the limitation of Strained-Si technology to the smaller gate length region (technology node) (Fig. 1).

A novel technique to fabricate 28 nm p-MOSFETs possessing gate oxide integrity on an embedded SiGe channel without silicon surface passivation

In the early development stage of 32nm processes, identifying and isolating systematic defects is critical to understanding the issues related to design and process interactions. Conventional inspection methodologies using random review sampling on large defect populations do not provide the information required to take accurate and quick corrective action. This paper demonstrates the successful identification and isolation of systematic defects using a novel methodology that combines Design Based Binning (DBB) and inline Defect Organizer (iDO). This new method of integrating design and defect data produced actionable inspection data, resulting in fewer mask revisions and reduced device development time.

Electrical Characteristics of MOSCAPs and the Effect of Postdeposition Annealing Temperatures

The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH/sub 3//N/sub 2/O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O/sub 2/-grown bottom oxide. In post-deposition treatment, increasing NH/sub 3/ nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N/sub 2/O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH/sub 3/ nitridation step.

Electrical characteristics of Al2O3/InSb MOSCAPs and the effect of postdeposition annealing temperatures

The characteristics of Al2O3/InSb MOSCAPs processed with different postdeposition annealing (PDA) temperatures are investigated. X-ray photoelectron spectroscopy analysis shows a significant reduction of InSb-oxides after HCl plus trimethyl aluminum treatment and oxide deposition. Multifrequency capacitance-voltage (C-V) characteristics exhibit low-frequency and asymmetrical C-V behaviors, in which capacitance in the InSb conduction band side is lower than in the valence band side. The electrical properties of the MOSCAPs are sensitive to PDA temperature and degraded significantly at PDA temperature >300 °C. This degradation is closely related to the diffusion of In, Sb into Al2O3 as indicated by transmission electron microscopy analyses.