Douglas Yu

Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n/sup +/ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E/sub OX/ at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E/sub OX/ to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.

A self-aligned airgap interconnect scheme

A new air-gap interconnect scheme with no additional patterning step successfully resolves the issue of unlanded via, and provides good interconnect reliability and improved packaging margin. We demonstrate that the insertion of airgaps in a very low-k dielectric (k=2.5) reduces the RC value of a 0.07um/0.07um comb structure by ∼14%, which is equivalent to an effective dielectric constant about 2.2.

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLPs high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.

InFO (Wafer Level Integrated Fan-Out) Technology

A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moores Law for the smart mobile as well as internet of things (IoT) applications.

A new integration technology platform: Integrated fan-out wafer-level-packaging for mobile applications

3D sub-system integration of logic and DRAM with TSV is desirable for wide memory bandwidth and reduced power for mobile applications. However, its manufacturing cost, along with testing and heat dissipation, remains to be outstanding issues. A new integration technology platform, InFO, is proposed to address it. In this paper, we compare three main 3D integration architectures: InFO_PoP, FC_PoP and 3DIC with TSV based on mobile product requirements, including system power- performance-profile (form factor), heat dissipation, memory bandwidth and production cycle-time along with cost. InFO not only best optimizes and achieves the requirements, but also more readily integrates partitioned-chips, which further impacts on the manufacturing of the logic/DRAM sub-system.

Methodology for analysis of TSV stress induced transistor variation and circuit performance

As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach.

Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications

Steady-state and transient thermal performance of a novel memory-integrated 3D-stacking packaging technology, integrated fan-out package-on-package (InFO_PoP), developed for state-of-the-art mobile applications were experimentally characterized using a specially designed thermal test vehicle. Two competing technologies, flip-chip PoP (FC_PoP) and 3DIC, are also included in this study as the reference for thermal performance benchmark. Direct thermal performance comparison is made possible by the data collected on the comparable FC_PoP thermal test vehicles. Thermal models have been successfully developed to enable further study on the cross-package performance comparison, as well as the impact of various key package design parameters. With the innovative approach replacing the organic substrate with thermally favorable RDL layers, a typical InFO_PoP package has 12% and 17% lower junction-to-ambient thermal resistance than a typical FC_PoP and 3DIC package, respectively. The appealing transient thermal response also makes the InFO_PoP the most competitive 3D packaging technology in high-performance mobile applications. Although the strong thermal interactions between the component packages of a PoP package complicates the thermal analysis, power envelop is proposed and demonstrated as a useful tool for package thermal design optimization. In addition, transient thermal analysis is recommended as a supplementary thermal design approach to the commonly used steady-state thermal analysis.

Generic rules to achieve bump electromigration immortality for 3D IC integration

An immortal solder micro-bump (μbump) electromigration (EM) lifetime has been demonstrated for 3D IC integration. This ultimate goal was achieved under strictly controlled conditions, including the optimal design of bump metallurgy, geometry, optimized processes, along with well-defined stressing conditions and manufacturing window. The current carrying capability and EM lifetime of μbump have been investigated as functions of stressing conditions which are correlated with the degradation mechanisms. When stressed under the appropriate g conditions, all μbump test samples survived prolonged stressing, some over 13,000 hours, without a failure. Cross-sectional analyses revealed that the entire solder joint almost all transformed into intermetallic compounds (IMCs) with very minor or no voids. The resistance plots showed an initial fast rise in resistance due to IMC formation, then gradually leveled off and eventually reached a steady state. The observed degradation mechanism is dominated by IMC formation, which is the same as that of the user conditions. On the other hand, void formation that eventually led to open failure was the dominant degradation mechanism when samples were aggressively stressed. In other words, when all other conditions were the same, the stressing conditions make a huge difference in determining between an almost immortal EM lifetime vs. a short lifetime using the same high quality μbumps. The boundary that separates the stressing conditions is roughly defined and will be discussed. In addition, since full IMC μbump will become inevitable in the future miniaturized solder interconnect structure, the EM behavior of IMC dominated μbump has also been evaluated in this study. Under highly accelerated stressing conditions of 174°C, at 1.6×105 A/cm2 current density, the IMC dominated μbumps were able to survive more than 600 hours and are still going strong. In comparison, solder μbump failed quickly after just 107 hours when stressed under the same condition. This comparison study clearly demonstrated that IMC dominated joint has significantly higher current carrying capability than that of the solder joint. After reviewing all the data, we have concluded that the failure criteria for solder μbump should be raised significantly higher than the 20% criteria traditionally used for the much larger C4 bumps.

Electromigration study of micro bumps at Si/Si interface in 3DIC package for 28nm technology and beyond

This paper is a study of the electromigration (EM) effects of micro bumps at silicon-silicon interface in 3DIC package for 28nm technology and beyond. Two joint schemes were designed and fabricated: one of the schemes was the joining of Sn-capped Cu post to ENEPIG (Electroless-Nickel-Electroless-Palladium-Immersion-Gold) UBM (Under-Bump-Metallurgy) pad on silicon substrate; the other scheme was the joining of top Cu post to bottom Cu post that formed a symmetrical joint structure. In-situ resistance was monitored to study the situation of joint degradation. During the test, a progressive resistance change was observed, which differed from the test data of conventional C4 (Controlled Collapse Chip Connections) bumps under regular test condition. (The detail will be described in this paper.) The experimental results showed that the rapid resistance shifts of both micro bump schemes were due to the high current density and the fast Cu-Sn IMC (Inter Metallic Compound) formation.

Advanced flip-chip package production solution for 40nm/28nm technology nodes

The key technology challenges and solutions in the packaging and assembly of large dies and/or fine pitch on organic substrates for both the 40 and 28 nm technology nodes are reported. Both eutectic PbSn, Pb-free solders, and Cu pillar bumps were used in the flip chip packages. The key challenge of chip-package-integrations (CPI) due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by the redesigning of the BEOL structure and optimizing the materials set including both the organic substrate and solder materials, along with process improvements.