Mo-Chiun Yu

Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n/sup +/ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E/sub OX/ at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E/sub OX/ to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.

A physical model for hole direct tunneling current in p/sup +/ poly-gate pMOSFETs with ultrathin gate oxides

A model of the hole direct tunneling gate current accounting for heavy and light holes subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO/sub 2/-Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass m/sub oxh/=0.51 M/sub o/ for the parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p/sup +/ poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lower barrier heights, and are prevailing over the first subbands for reducing the oxide field down below 1 MV/cm.

Downscaling limit of equivalent oxide thickness in formation of ultrathin gate dielectric by thermal-enhanced remote plasma nitridation

The gate-oxide downscaling limit in thermal-enhanced remote plasma nitridation (RPN) process for forming ultrathin gate dielectric has been extensively investigated. In this work, the radical-induced re-oxidation effect has been observed as the base-oxide thickness less than 20 /spl Aring/. Nevertheless, for the base-oxide thickness thicker than 17 /spl Aring/, the RPN process still can effectively reduce the equivalent oxide thickness (EOT) and almost no transconductance degradation is observed. Further thinning of the base oxide will degrade the reduction of EOT and the transconductance with the RPN process, due to the penetration of nitrogen radicals into the active region. The physical and electrical properties of the ultrathin oxides (10 /spl sim/ 20 /spl Aring/) affected by this radical penetration have been studied extensively as well. Finally, the thinnest thickness has been estimated by compromising the feasible base-oxide thickness, the degradation of device performance, and the gate leakage criteria. Based on the forementioned criteria, we rind the 14 /spl Aring/ EOT to be the downscaling limit of the gate-oxide thickness.

The effect of remote plasma nitridation on the integrity of the ultrathin gate dielectric films in 0.13 μm CMOS technology and beyond

The authors report the effect of the remote plasma nitridation (RPN) process on characteristics of ultrathin gate dielectric CMOSFETs with the thickness in the range of 18 /spl Aring//spl sim/22 /spl Aring/. In addition, the effect of RPN temperature on the nitrogen-profile within the gate dielectric films has been investigated. Experimental results show that the thinner the gate dielectric films, the more significant effect on reducing the gate current and thinning the thickness of gate dielectric films by the RPN process. Furthermore, the minimum dielectric thickness to block the penetration of B and N has been estimated based on the experimental results. The minimum RPN gate dielectric thickness is about 12 /spl Aring/.

Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion

Ultrathin thermally enhanced remote plasma nitrided oxides (TE-RPNO) with equivalent oxide thickness down to 1.65 nm are fabricated to investigate their leakage current reduction and boron diffusion barrier performances. A PMOSFET with TE-RPNO, compared to its conventional oxide counter-part, yields almost one order magnitude lower gate leakage current, less flatband voltage changes in high boron implantation dose or activation temperature, and shows broader process windows in the tradeoff between boron penetration and dopant activation.

High-quality ultrathin (1.6 nm) nitride/oxide stack gate dielectrics prepared by combining remote plasma nitridation and LPCVD technologies

Ultrathin nitride/oxide (N/O) gate dielectric stacks with equivalent oxide thickness of 1.6 nm have been fabricated by combining remote plasma nitridation (RPN) and low pressure chemical vapor deposition (LPCVD) technologies. NMOSFETs with these gate stacks exhibit good interface properties, improved subthreshold characteristics, low off-state currents, enhanced reliability, and about one order of magnitude reduction in gate leakage current to their oxide counterparts.

Edge hole direct tunneling in off-state ultrathin gate oxide p-channel MOSFETs

This paper examines the edge direct tunneling (EDT) of hole from p+ polysilicon to underlying p-type drain extension in off-state p-channel MOSFETs having ultrathin gate oxide thicknesses (1.2-2.2 nm). It is found that for thinner oxide thicknesses, hole EDT is more pronounced over the conventional GIDL and gate-to-channel tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model accounting for heavy and light holes subbands in the quantized accumulation polysilicon surface is built explicitly. This model consistently reproduces EDT I-V and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.

Modeling of the gate leakage current reduction in MOSFET with ultra-thin nitrided gate oxide

Abstract The origins of different gate leakage behaviors for both PMOS and NMOS with ultra-thin nitrided gate oxide have been studied and modeled. Both equivalent oxide thickness (EOT) and barrier lowering are affected the gate leakage. In NMOS with nitrided oxide, the advantage of EOT decrease is larger to offset the barrier lowering, thus improvement on gate current reduction rate ( R J g ). The situation in PMOS is just contrary to the NMOS, therefore the gate leakage increased with increasing nitridation time. We attribute this to the different barrier lowering in conduction band and valence band.

Base oxide scaling limit of thermally-enhanced remote plasma nitridation (TE-RPN) process for ultra-thin gate dielectric formation

We investigate the scaling limit of base oxides treated by thermally-enhanced remote plasma nitridation (TE-RPN) for ultra-thin gate dielectric formation. Under optimized RPN conditions, this work shows gate-dielectric equivalent thickness (EOT) scalability and no transconductance degradation are characteristic of processes with base oxide thickness down to 17 /spl Aring/. Thinner base oxides result in reduced EOT scalability and transconductance degradation, resulting in /spl sim/14 /spl Aring/ manufacturable EOT limit for TE-RPN gate dielectrics.

Improved current drivability and poly-gate depletion of submicron PMOSFET with poly-SiGe gate and ultra-thin nitride gate dielectric

Abstract The electrical properties of poly-SiGe gated PMOSFETs have been investigated and compared to the conventional poly-Si gated device. Both types of PMOSFETs use ultra-thin nitride gate dielectric. Poly-SiGe gated devices exhibit 10% higher inversion capacitance, improved subthreshold properties, and superior current drivability. The improvements are contributed to the suppression of the poly-gated depletion effect and the enhanced carrier mobility.