Hyun J. Shin

Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits

Driver configurations and full-swing techniques for several types of BiCMOS logic circuits are compared to examine their performance in scaled technologies. Of the three driver configurations (common emitter, gated diode, and emitter follower) analyzed, the emitter-follower type is most advantageous for scale power-supply voltage circuits. Full-swing techniques boost the circuit performance, and base-emitter shunting is more favorable than collector-emitter shunting. >

Single chip 4/spl times/500 Mbaud CMOS transceiver

This CMOS chip replaces a 72-wire interface with 4 serial, duplex links, for relief of interconnect congestion in applications such as large switching systems. The design supports transmission at 1.6 Gb/s per direction in full-duplex mode and provides the user with a transparent interface. The data source provides fixed-length synchronous packets segmented into 4 parallel bytes along with parity and flag bits. The packet size can be programmed up to 4/spl times/64 B with a parameter loaded from an external controller. Data packets can he transmitted contiguously. During idle periods that are marked by a flag, the circuit generates and transmits fill packets, which start with a non-data Comma character. The Comma marks both byte and packet boundaries on a serial link. The Fill packets carry an idle sequence or diagnostic and control information such as Not Operational, Remote Wrap, or Unwrap. Each link carries 400 Mb/s, corresponding to 500 Mbaud after 8 B/10 B encoding.

A 4 b 8 GSample/s A/D converter in SiGe bipolar technology

A 4 b flash-type A/D converter (ADC) with pipelined encoder has been implemented in a SiGe bipolar technology for very high-frequency mixed-signal applications. The chip is fully functional at 8 GSample/s. Maximum input bandwidth is 4 GHz based on beat frequency measurements. Both DNL and INL are within 0.25 LSB. The chip includes over 1000 transistors and consumes 500mW at 3.6V.

Low-dropout on-chip voltage regulator for low-power circuits

A series-type, on-chip voltage regulator generates 2.5 V from a 3.3-V supply for low-power ICs implemented in a scaled, low-voltage, 0.25-/spl mu/m CMOS technology. The gate of the n-channel regulating MOSFET is boosted above the given supply voltage to enable low-dropout regulation.

High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage

The design of an ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array applications is presented. The circuit features an AC-coupled dynamic current source to improve the power-delay of the logic stage (current switch). A self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8- mu m double-poly, self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.62* (1.90*) improvement in the speed (load driving capability) of a loaded gate compared with the conventional ECL circuit. >

A 500 Mb/s, 20-channel CMOS laser diode array driver for a parallel optical bus

For the ever-increasing demand of communication bandwidth for clustered computer interconnections, parallel optical bus technology provides a small, lightweight, flexible and low-cost alternative to the existing technology. A 20-channel, 500 Mb/s/channel CMOS laser diode (LD) driver drives a vertical cavity surface emitting laser (VCSEL) array in a parallel optical bus transmitter. It has a 500 Mb/s low voltage differential signal (LVDS) input interface with wide input common mode range. Total data throughput is 10 Gb/s. It uses a standard 3.3 V power supply with 1.6 W of power dissipation, with user features such as on-chip data scrambling and built-in link self-test.

A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits

A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the emitter-follower input from the logic stage. Simulation results based on a 0.5-/spl mu/m advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively. >

An experimental 5-Gb/s 16*16 Si-bipolar crosspoint switch

An experimental 16*16, nonblocking, asynchronous crosspoint switch with a data rate of 5-Gb/s per channel is presented. Implemented in a 0.8- mu m, double-poly, self-aligned Si-bipolar ECL technology, the 3-mm*3-mm chip, featuring a multiplexer-type architecture with a three-device crosspoint cell, demonstrates a nominal data path delay of 420 ps with 12.5-ps RMS jitter and a setup time of 1 ns and dissipates about 4.6 W. >

Full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration

Various full-swing BiCMOS logic circuits with complementary emitter-follower driver configurations are described. The performance of the circuits is demonstrated in a 1.2 mu m complementary BiCMOS technology with a 6 GHz n-p-n and a 2 GHz p-n-p transistor. For the basic circuit, gate delay (fan-in=2, fan-out=1) is 366 ps and driving capability is 288 ps/pF at 4 V. Delay-power tradeoffs that depend on characteristics of the clamping diode between two base nodes of the complementary emitter-follower driver, parasitic capacitances at the two base nodes, and a technique that can be used to achieve full swing have been identified for these circuits. These circuits show leverage over the conventional BiCMOS circuit for reduced power-supply voltages. >

A 5 Gb/s 16*16 Si-bipolar crosspoint switch

An experimental 16*16, nonblocking, asynchronous crosspoint switch with 5 Gb/s channel data rate is described. Implemented in a 0.8- mu m, double-poly, self-aligned Si-bipolar ECL (emitter coupled logic) technology, the 3*3 mm/sup 2/ chip with a multiplexer-type architecture and a three-device crosspoint cell features a data path delay of 420 ps and a set-up time of 1 ns, and dissipates about 4.6 W. Signal levels are ECL compatible. This crosspoint which supports selective or full broadcasting and a simple expansion mechanism.<<ETX>>